[Bug 101283] skylake: page fault accessing address 0

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https://bugs.freedesktop.org/show_bug.cgi?id=101283

            Bug ID: 101283
           Summary: skylake: page fault accessing address 0
           Product: Mesa
           Version: 17.0
          Hardware: Other
                OS: All
            Status: NEW
          Severity: normal
          Priority: medium
         Component: Drivers/Vulkan/intel
          Assignee: intel-3d-bugs at lists.freedesktop.org
          Reporter: cstout at chromium.org
        QA Contact: intel-3d-bugs at lists.freedesktop.org
                CC: jason at jlekstrand.net

The function blorp_emit_gen8_hiz_op contains a pipe control operation that has
only the WriteImmediateData bit set.  It doesn't specify an address, so this
results in a store to address 0.

a) What is this pipe control for?  I don't see the need for it in the docs.

>From what I can see, the docs for 3DSTATE_WM_HZ_OP say: "As this command
generates an implicit rectangle, SW must make sure any MMIO register writes
following WM_HZ_OP must be preceded by PIPE_CONTROL with Command Streamer Stall
Enable bit set."

In the code there's a following PIPECONTROL with depth_stall and depth flush
bits set, which corresponds to the docs in the section 'Depth Buffer Clear'.

b) How is it not a problem to emit a pipecontrol that writes to address 0?

Thanks.

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