[Bug 103115] [BSW BXT GLK] dEQP-VK.spirv_assembly.instruction.compute.sconvert.int32_to_int64
bugzilla-daemon at freedesktop.org
bugzilla-daemon at freedesktop.org
Thu Oct 5 19:57:06 UTC 2017
https://bugs.freedesktop.org/show_bug.cgi?id=103115
Bug ID: 103115
Summary: [BSW BXT GLK]
dEQP-VK.spirv_assembly.instruction.compute.sconvert.in
t32_to_int64
Product: Mesa
Version: git
Hardware: Other
OS: All
Status: NEW
Severity: normal
Priority: medium
Component: Drivers/DRI/i965
Assignee: intel-3d-bugs at lists.freedesktop.org
Reporter: mark.a.janes at intel.com
QA Contact: intel-3d-bugs at lists.freedesktop.org
This test and three others regressed at
mesa 2572c2771d0cab0b9bc489d354ede44dfc88547b
Author: Matt Turner <mattst88 at gmail.com>
i965: Validate "Special Requirements for Handling Double Precision Data Types"
I did not implement:
CNL's restriction on 64-bit int + align16, because I don't think
we'll ever use this combination regardless of hardware generation.
The restriction on immediate DF -> F conversions, because there's no
reason to ever generate that, and I don't even know how DF -> F
conversions are supposed to work in Align16 since (1) the dst stride
must be 1, but (2) the dst stride would have to be 2 for src and dst
strides to be aligned.
---------------------------------------------
dEQP-VK.spirv_assembly.instruction.compute.sconvert.int32_to_int64
dEQP-VK.spirv_assembly.instruction.compute.sconvert.int32_to_uint64
dEQP-VK.spirv_assembly.instruction.compute.uconvert.uint32_to_uint64
+dEQP-VK.spirv_assembly.instruction.compute.uconvert.uint32_to_int64
deqp-vk:
/home/jenkins/workspace/Leeroy_2/repos/mesa/src/intel/compiler/brw_fs_generator.cpp:2203:
int fs_generator::generate_code(const cfg_t*, int): Assertion `validated'
failed.
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