[Bug 68040] New: [HSW desktop/mobile bisected]WARNING: at drivers/gpu/drm/i915/i915_gem.c:3440 i915_gem_object_set_cache_level+0x1bd/0x1dc [i915]()

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=68040

          Priority: medium
            Bug ID: 68040
          Assignee: chris at chris-wilson.co.uk
           Summary: [HSW desktop/mobile bisected]WARNING: at
                    drivers/gpu/drm/i915/i915_gem.c:3440
                    i915_gem_object_set_cache_level+0x1bd/0x1dc [i915]()
        QA Contact: intel-gfx-bugs at lists.freedesktop.org
          Severity: major
    Classification: Unclassified
                OS: All
          Reporter: cancan.feng at intel.com
          Hardware: Other
            Status: NEW
           Version: unspecified
         Component: DRM/Intel
           Product: DRI

System Environment:
--------------------------------------------
Kernel: (drm-intel-next-queued)b8a1868b10bb4fe7fb7d283da5d56064b1a189f4
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date:   Thu Aug 8 14:41:11 2013 +0100

    drm/i915: Allow the user to set bo into the DISPLAY cache domain

Bug detailed description:
--------------------------------------------
System boots with WARNING like this:

[    1.168965] WARNING: CPU: 1 PID: 1258 at
drivers/gpu/drm/i915/i915_gem.c:3440
i915_gem_object_set_cache_level+0x1bd/0x1dc [i915]()

Bisected info:

d46f1c3f1372e3a72fab97c60480aa4a1084387f is the first bad commit
commit d46f1c3f1372e3a72fab97c60480aa4a1084387f
Author:     Chris Wilson <chris at chris-wilson.co.uk>
AuthorDate: Thu Aug 8 14:41:06 2013 +0100
Commit:     Daniel Vetter <daniel.vetter at ffwll.ch>
CommitDate: Sat Aug 10 11:24:18 2013 +0200

    drm/i915: Allow the GPU to cache stolen memory

    As a corollary to reviewing the interaction between LLC and our cache
    domains, the GPU PTE bits are independent of the CPU PAT bits. As such
    we can set the cache level on stolen memory based on how we wish the GPU
    to cache accesses to it. So we are free to set the same default cache
    levels as for normal bo, i.e. enable LLC cacheing by default where
    appropriate.

    Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
    Reviewed-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
    Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>

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