[Bug 66808] [HSW Bisected]igt/kms_flip/blocking-absolute-wf_vblank due to power well enabled by default

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=66808

--- Comment #10 from Paulo Zanoni <przanoni at gmail.com> ---
(In reply to comment #9)
> For the very first time we run the test on pipe B, it works. After the power
> well is reset for the first time, the test on pipe B starts to fail and
> keeps failing forever.
> 
> Considering that the problem doesn't happen with i915.disable_power_well=0,
> I wonder if the bug is related to the fact that the pipe counters go back to
> 0 after we disable the power well (PIPE_FRMCNT, etc). Or maybe it's related
> to other registers that get reset.

Yeah, if I set dev->last_vblank[1] = 0; and dev->last_vblank[2] = 0; at the
!enable case inside __intel_set_power_well, the problem goes away. Now we need
to discover what's the correct way to reset these counters without messing with
the drm helpers or the vblank locking.

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