[Bug 59841] Internal display not shown with intel X driver
bugzilla-daemon at bugzilla.kernel.org
bugzilla-daemon at bugzilla.kernel.org
Tue Jun 18 12:45:40 PDT 2013
https://bugzilla.kernel.org/show_bug.cgi?id=59841
--- Comment #12 from jkp <jkp at iki.fi> 2013-06-18 19:45:40 ---
Looks like it's a matter of code execution order, that the intention was to
keep the clamping code (sans the debug message) but the different execution
order breaks things at least for this computer. This patch fixes it for me with
3.10-rc2. I'll test with a later kernel.
# diff -c intel_dp.c.virgin intel_dp.c
*** intel_dp.c.virgin 2013-05-21 00:37:38.000000000 +0300
--- intel_dp.c 2013-06-18 22:42:44.404142315 +0300
***************
*** 702,709 ****
/* Walk through all bpp values. Luckily they're all nicely spaced with 2
* bpc in between. */
bpp = min_t(int, 8*3, pipe_config->pipe_bpp);
- if (is_edp(intel_dp) && dev_priv->edp.bpp)
- bpp = min_t(int, bpp, dev_priv->edp.bpp);
for (; bpp >= 6*3; bpp -= 2*3) {
mode_rate = intel_dp_link_required(target_clock, bpp);
--- 702,707 ----
***************
*** 742,748 ****
intel_dp->link_bw = bws[clock];
intel_dp->lane_count = lane_count;
adjusted_mode->clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
- pipe_config->pipe_bpp = bpp;
pipe_config->pixel_target_clock = target_clock;
DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
--- 740,745 ----
***************
*** 755,760 ****
--- 752,761 ----
target_clock, adjusted_mode->clock,
&pipe_config->dp_m_n);
+ if (is_edp(intel_dp) && dev_priv->edp.bpp)
+ bpp = min_t(int, bpp, dev_priv->edp.bpp);
+ pipe_config->pipe_bpp = bpp;
+
return true;
}
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