[Bug 80701] [BYT Regression]igt/kms_flip subcases cause "WARNING: CPU: 0 PID: 3943 at drivers/gpu/drm/i915/intel_dp.c:3092 intel_dp_complete_link_train+0x100/0x27f [i915]()" sporadically

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=80701

Guo Jinxian <jinxianx.guo at intel.com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Keywords|bisect_pending              |

--- Comment #1 from Guo Jinxian <jinxianx.guo at intel.com> ---
bfafe93a1cd466ef318b7e5f6c65f59aee147791 is the first bad commit
commit bfafe93a1cd466ef318b7e5f6c65f59aee147791
Author:     Imre Deak <imre.deak at intel.com>
AuthorDate: Thu Jun 5 20:31:47 2014 +0300
Commit:     Jani Nikula <jani.nikula at intel.com>
CommitDate: Mon Jun 23 10:02:03 2014 +0300


    drm/i915: cache hw power well enabled state

    Jesse noticed that the punit communication needed to query the VLV power
    well status can cause substantial delays. Since we can query the state
    frequently, for example during I2C transfers, maintain a cached version
    of the HW state to get rid of this delay.

    This fixes at least one reported regression where boot time increased by
    ~4 seconds due to frequent power well state queries on VLV during eDP
    EDID read.

    This regression has been introduced in

    commit bb4932c4f17b68f34645ffbcf845e4c29d17290b
    Author: Imre Deak <imre.deak at intel.com>
    Date:   Mon Apr 14 20:24:33 2014 +0300

        drm/i915: vlv: check port power domain instead of only D0 for eDP VDD
on

    Reported-by: Jesse Barnes <jesse.barnes at intel.com>
    Signed-off-by: Imre Deak <imre.deak at intel.com>
    Reviewed-by: Jesse Barnes <jbarnes at virtuousgeek.org>
    Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>

:040000 040000 fbc81acdbc7a7c97390719fc5d5d71fb24e11901
3663f8be487a862dd1c710521a17b2c61a6963c5 M   drivers

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