[Bug 74955] [HSW Regression]boot system has <3>[ 1.627079] [drm:intel_pipe_config_compare] *ERROR* mismatch in port_clock (expected 146250, found 270000)

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=74955

Ville Syrjala <ville.syrjala at linux.intel.com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|NEW                         |RESOLVED
         Resolution|---                         |FIXED

--- Comment #6 from Ville Syrjala <ville.syrjala at linux.intel.com> ---
Fixed by

commit 8f7abfd82246a8d8b5bd1ad3056f3b46345b6b4a
Author: Ville Syrjälä <ville.syrjala at linux.intel.com>
Date:   Thu Feb 27 14:23:12 2014 +0200

    drm/i915: Fix DDI port_clock for VGA output

    On DDI there's no PLL as such to generate the pixel clock for VGA.
    Instead we derive the pixel clock from the FDI link frequency. So
    to make .compute_config match what .get_config does, we need to
    set the port_clock based on the FDI link frequency.

    Note that we don't even check the port_clock when selecting the
    PLL for VGA output. We just assume SPLL at 1.35GHz is what we want,
    and that does match with the asumption of FDI frequency of 2.7Ghz
    we have in intel_fdi_link_freq().

    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=74955
    Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
    Reviewed-by: Paulo Zanoni <paulo.r.zanoni at intel.com>
    Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>

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