[Bug 85327] [HSW] GPU hang on HSW Celeron when doing 16 VA-API decodes and compositing
bugzilla-daemon at freedesktop.org
bugzilla-daemon at freedesktop.org
Wed Oct 22 07:20:47 PDT 2014
https://bugs.freedesktop.org/show_bug.cgi?id=85327
--- Comment #5 from Simon Farnsworth <simon at farnz.org.uk> ---
Created attachment 108234
--> https://bugs.freedesktop.org/attachment.cgi?id=108234&action=edit
Error state after patch from comment #3 is applied
No luck with that patch - it appears to simply move the deckchairs around
again. New error state attached.
I note from the OSRC PRMs that your patch strictly speaking asks the GPU to do
something that's claimed as not supported - you set DW1 bit 20 (CS stall), but
not one of the 5 bits the OSRC PRMs claim you must also set (at least one of
DW1 bits 12, 0, 1, 13 or 15:14 must be set).
--
You are receiving this mail because:
You are the QA Contact for the bug.
You are on the CC list for the bug.
You are the assignee for the bug.
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.freedesktop.org/archives/intel-gfx-bugs/attachments/20141022/ffce27b4/attachment.html>
More information about the intel-gfx-bugs
mailing list