[Bug 83497] [BDW] Pipe A FIFO underrun errors with a 4k display

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=83497

--- Comment #3 from Jani Nikula <jani.nikula at intel.com> ---
(In reply to comment #1)
> There's a known corruption case with IPS when dotclock >
> 95% cdclock (which can happen here as you have an eDP 4k display, so IPS
> should be running)

Bspec says, "Do not enable IPS when the pipe pixel rate is greater than 95% of
the CDCLK frequency." IOW, IPS should *not* be running in this case. I presume
the missing check should be added to hsw_compute_ips_config().

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