[Bug 84265] [BSW Regression]System fails to find eDP monitor.

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=84265

liulei <lei.a.liu at intel.com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Keywords|bisect_pending              |bisected

--- Comment #6 from liulei <lei.a.liu at intel.com> ---
According my bisect, it's a complex issue.
+--------------------------------------+------------+
|    commit     |            status    |    date    |
+--------------------------------------+    early   |
|   7895a81d    |          works       |      |     |
+--------------------------------------+      |     |
|   d7f25f23    |   render error       |      |     |
+--------------------------------------+      |     |
|   c8f7a0db    |  render error + hang |      |     |
+--------------------------------------+      |     |
|   84fd4f4e    |  Black screen + hang |      |     |
+--------------------------------------+     \|/    |
|   d2152b25    |  Black screen        |    latest  |
+---------------------------------------------------+

All commits above table except first one are first bad commit. I list commit
detail.
commit d2152b2524a96e6cb71097ea26c2e7c3f9e3ee12
Author:     Ville Syrjälä <ville.syrjala at linux.intel.com>
AuthorDate: Mon Apr 28 14:15:24 2014 +0300
Commit:     Daniel Vetter <daniel.vetter at ffwll.ch>
CommitDate: Tue May 20 15:43:18 2014 +0200

    drm/i915/chv: Set soft reset override bit for data lane resets

    The bits we've been setting so far only progagate the reset singal to
    the data lanes. To actaully force the reset signal we need to set another
    override bit.

    v2: Fix mispalced ';' (Mika)

commit 84fd4f4e18885fc6b4a00f222040f24727b52514
Author:     Rafael Barbalho <rafael.barbalho at intel.com>
AuthorDate: Mon Apr 28 14:00:42 2014 +0300
Commit:     Daniel Vetter <daniel.vetter at ffwll.ch>
CommitDate: Tue May 20 15:22:36 2014 +0200

    drm/i915/chv: Add CHV display support

    Add support for the third pipe in cherrview

    v2: Don't use spaces for indentation (Jani)
        Wrap long lines

commit c8f7a0dbd7bfb9719d281407587f78c84f0411e6
Author:     Daniel Vetter <daniel.vetter at ffwll.ch>
AuthorDate: Thu Apr 24 23:55:04 2014 +0200
Commit:     Daniel Vetter <daniel.vetter at ffwll.ch>
CommitDate: Mon May 19 15:31:06 2014 +0200

    drm/i915: Inline set_base into crtc_mode_set

    A lot of the code in set_base is uncessary when the crtc is off, so we
    can get rid of it all. Also, we don't need to call the fbc/psr update
    functions since the crtc enable/disable hooks do that already.

    The only things we really need are:
    - Pin the new framebuffer and potentially unpin the old framebuffer
      (if the crtc has been on and we only change the configuration).
    - Update the plane registers.

    The first step will move out of platform code with the very next
    patch.

    v2: Don't forget about haswell ...

commit d7f25f23d2e0c7898c95b2a6fd84f6358588de48
Author:     Damien Lespiau <damien.lespiau at intel.com>
AuthorDate: Thu May 8 22:19:40 2014 +0300
Commit:     Daniel Vetter <daniel.vetter at ffwll.ch>
CommitDate: Tue May 13 14:13:22 2014 +0200

    drm/i915/chv: Implement stolen memory size detection

    CHV uses the same bits as SNB/VLV to code the Graphics Mode Select field
    (GFX stolen memory size) with the addition of finer granularity modes:
    4MB increments from 0x11 (8MB) to 0x1d.

    Values strictly above 0x1d are either reserved or not supported.

    v2: 4MB increments, not 8MB. 32MB has been omitted from the list of new
        values (Ville Syrjälä)

    v3: Also correctly interpret GGMS (GTT Graphics Memory Size) (Ville
        Syrjälä)

    v4: Don't assign a value that needs 20bits or more to a u16 (Rafael
        Barbalho)

    [vsyrjala: v5: Split the early quirks to another patch]

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