[Bug 88191] [PNV Bisected]igt/gem_exec_big fails

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=88191

--- Comment #7 from Chris Wilson <chris at chris-wilson.co.uk> ---
Oh, and while I remember. The bug is clearly independent of 43566dedd, but
because of the mb() inside set-to-gtt-domain we conveniently masked this bug
i.e. the impact of the bug is non-existent, though it is probably the real
reason why I had to add the mb() there in the first place. That's for a latter
patch.

Oh, indeedy....

commit 63256ec5347fb2344a42adbae732b90603c92f35
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date:   Tue Jan 4 18:42:07 2011 +0000

    drm/i915: Enforce write ordering through the GTT

    We need to ensure that writes through the GTT land before any
    modification to the MMIO registers and so must impose a mandatory write
    barrier when flushing the GTT domain. This was revealed by relaxing the
    write ordering by experimentally mapping the registers and the GATT as
    write-combining.

commit d0a57789d5ec807fc218151b2fb2de4da30fbef5
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date:   Tue Oct 9 19:24:37 2012 +0100

    drm/i915: Only insert the mb() before updating the fence parameter

    With a fence, we only need to insert a memory barrier around the actual
    fence alteration for CPU accesses through the GTT. Performing the
    barrier in flush-fence was inserting unnecessary and expensive barriers
    for never fenced objects.

    Note removing the barriers from flush-fence, which was effectively a
    barrier before every direct access through the GTT, revealed that we
    where missing a barrier before the first access through the GTT. Lack of
    that barrier was sufficient to cause GPU hangs.


Bingo.

-- 
You are receiving this mail because:
You are the QA Contact for the bug.
You are on the CC list for the bug.
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.freedesktop.org/archives/intel-gfx-bugs/attachments/20150108/83090e25/attachment-0001.html>