[Bug 89661] [ivb] Unable to configure 3rd pipe (e.g. LVDS + DP + DP)

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=89661

xuan--2010--bugs.freedesktop.org at baldauf.org changed:

           What    |Removed                     |Added
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                 CC|                            |xuan--2010--bugs.freedeskto
                   |                            |p.org at baldauf.org

--- Comment #23 from xuan--2010--bugs.freedesktop.org at baldauf.org ---
I, too, encounter this bug on HD 4000. Note that this bug only seems to surface
with LVDS+DP+DP, even if both DP pixel clocks are identical. It does not happen
with LVDS+DVI+DVI or LVDS+HDMI+HDMI (where the DVI or HDMI pixel clocks are
identical). (However, HDMI is not an option due to the lack of HDMI inputs at
my monitors and the need for a high pixel clock due to high monitor resolution.
The HDMI pixel clock limit seems to be around 225 MHz, while the effective DP
pixel clock limit seems to be around 395 MHz.)

Apparently, PLL sharing works for HDMI+HDMI, but PLL sharing does not work for
DP, while it should also work for DP+DP.

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