[Bug 95476] [BXT-P] i915 driver overwrites the DDI PHY register for the 1366x768 panel with incorrect values

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=95476

--- Comment #3 from Imre Deak <imre.deak at intel.com> ---
(In reply to Jani Nikula from comment #2)
> (In reply to Tarun Vyas from comment #0)
> > In the APL platforms, the firmware enables the 1366x768 panels by correctly
> > programming the DDI PHY registers, but this leads to a PHY state mismatch
> > according to the i915 driver because the driver expects to read a value from
> > the PHY registers that differs from what was programmed by the firmware.
> > Hence, the i915 driver goes ahead and reprograms the PHY, incorrectly,
> > causing the DP link training to fail. The i915 driver will need
> > modifications to correct this behavior. Filing this bug to track those
> > modifications.
> 
> I get the impression you know where things go wrong; can you give more
> specifics please?
> 
> Alternatively, please add 'intel_reg dump' output before and after loading
> the i915 driver, i.e. register dumps with the values programmed by firmware
> and i915, respectively.
> 
> The intel_reg tool is part of the intel-gpu-tools package 
> http://cgit.freedesktop.org/xorg/app/intel-gpu-tools/

The problem is caused by incorrect PHY lane staggering setup, not matching the
eDP lane configuration. I'm working on a solution that moves the PHY setup
later where we know already the eDP lane config, so can program the staggering
properly.

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