[Bug 97244] [SKL] 5k tiled monitor DP sync issues

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=97244

--- Comment #6 from Andrew Snow <andrew at modulus.org> ---

Same problem here with Dell 5K and a Skylake i915 cpu/gpu.

I think the problem is that the intel driver is assigning seperate PLLs for
each port.  The capability exists to share a common PLL clock source for both
ports.

I suspect the Windows driver sees both ports have the same resolution and
framerate and shares a PLL automatically.

Is there a way to force PLL sharing to test this theory?

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