[Bug 97965] [BSW] External HDMI monitor suddenly shows solid color when playing Youtube video at 1080p [fifo underrun]

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=97965

--- Comment #42 from Yu Kang Ku <ykku16dev2 at gmail.com> ---
(In reply to Ville Syrjala from comment #39)
> (In reply to Yu Kang Ku from comment #38)
> > (In reply to Ville Syrjala from comment #37)
> > > Can we repeat the failure with, say, only pipe B active + DDR DVFS disabled
> > > + PM5 disabled + cxsr/maxfifo disabled + trickle feed enabled?

I was finally able to simulate "closing the lid" on the BSW RVP and carry out
the experiment you requested.  Unfortunately, the problem is still
reproducible.

The output of intel_watermark is here:
https://bugs.freedesktop.org/attachment.cgi?id=127636

The output of intel_reg dump --all is here:
https://bugs.freedesktop.org/attachment.cgi?id=127637

These outputs show that the conditions you specified have been met.

The following are the code changes I made to meet the conditions that you
specified:

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 5d39ad2..35766b7 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -946,7 +946,7 @@ static void vlv_setup_wm_latency(struct drm_device *dev)

        dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;

-       if (IS_CHERRYVIEW(dev_priv)) {
+       if (0 && IS_CHERRYVIEW(dev_priv)) {
                dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
                dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;

@@ -1288,7 +1288,7 @@ static void vlv_merge_wm(struct drm_device *dev,
        int num_active_crtcs = 0;

        wm->level = to_i915(dev)->wm.max_level;
-       wm->cxsr = true;
+       wm->cxsr = false;

        for_each_intel_crtc(dev, crtc) {
                const struct vlv_wm_state *wm_state = &crtc->wm_state;

diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 6c11168..10d6eac 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -1070,7 +1070,7 @@ static void vlv_init_display_clock_gating(struct
drm_i915_private *dev_priv)
        /*
         * Disable trickle feed and enable pnd deadline calculation
         */
-       I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
+       I915_WRITE(MI_ARB_VLV, 0);
        I915_WRITE(CBR1_VLV, 0);

        WARN_ON(dev_priv->rawclk_freq == 0);

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