[Bug 100047] [IGT] [SKL/GLK/APL/BSW] kms_sysfs_edid_timing test assertion failure

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=100047

--- Comment #10 from Clinton Taylor <clinton.a.taylor at intel.com> ---
comment #8 should read 1ms between 8 byte reads as seen in the scope shot
attached.

DDC operates at 100 Khz clock rate and AUX at 1 Mhz. eDP also only reads 128
bytes total compared to HDMI/DP reads of 256 or 512 bytes. 

Are we sure 50ms is a valid test for DDC traffic?

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