[Bug 97244] [SKL] 5k tiled monitor DP sync issues

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=97244

--- Comment #19 from Jani Nikula <jani.nikula at intel.com> ---
(In reply to Andrew Snow from comment #6)
> Same problem here with Dell 5K and a Skylake i915 cpu/gpu.
> 
> I think the problem is that the intel driver is assigning seperate PLLs for
> each port.  The capability exists to share a common PLL clock source for
> both ports.
> 
> I suspect the Windows driver sees both ports have the same resolution and
> framerate and shares a PLL automatically.

If anyone does have the hardware and Windows readily available, dumping the PCI
MMIO BAR on Windows would let us check how it configures the hardware in this
case. Alas, I have no idea what the tool for dumping it is.

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