[Bug 105771] [CI] igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a - dmesg-warn - *ERROR* timeout during PHY0 power on

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=105771

--- Comment #7 from Imre Deak <imre.deak at intel.com> ---
Hm, the logs don't seem to match the change in the fix:

(In reply to Marta Löfstedt from comment #5)
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_4040/shard-glk5/
> igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
> 
> [  172.683710] [drm:_bxt_ddi_phy_init [i915]] *ERROR* timeout during PHY0
> power on
> 
> The patch was integrated to CI_DRM_4039, so it doesn't seem that the fix is
> enough.

<7>[  172.683181] [drm:intel_power_well_enable [i915]] enabling dpio-common-b
<3>[  172.683710] [drm:_bxt_ddi_phy_init [i915]] *ERROR* timeout during PHY0
power on

The wait here was maximum ~600usec, as opposed to the minimum of 1msec we
should have after the fix.

(In reply to Marta Löfstedt from comment #6)
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_4043/shard-glk5/
> igt at gem_exec_suspend@basic-s3.html
> 
> [  148.463532] [drm:_bxt_ddi_phy_init [i915]] *ERROR* timeout during PHY0
> power on

<7>[  148.463053] [drm:intel_power_well_enable [i915]] enabling dpio-common-b
<3>[  148.463532] [drm:_bxt_ddi_phy_init [i915]] *ERROR* timeout during PHY0
power on

The wait here was maximum ~500usec instead of the minimum of 1msec. 

The only explanation for this I have is that either that the system clock is
off somehow, or that these CI runs were without the fix applied.

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