[PATCH 38/38] bsw-irq4

[Chris Wilson]

---
 drivers/gpu/drm/i915/i915_irq.c | 34 ++++++++++++++++++++--------------
 1 file changed, 20 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 4e58737827f0..496c9c186857 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1830,6 +1830,7 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
 		u32 iir, gt_iir, pm_iir;
 		u32 pipe_stats[I915_MAX_PIPES];
 		u32 hotplug_status = 0;
+		bool has_pipe_stats;
 		u32 ier = 0;
 
 		gt_iir = I915_READ(GTIIR);
@@ -1868,7 +1869,8 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
 
 		/* Call regardless, as some status bits might not be
 		 * signalled in iir */
-		valleyview_pipestat_irq_ack(dev_priv, iir, pipe_stats);
+		has_pipe_stats = 
+			valleyview_pipestat_irq_ack(dev_priv, iir, pipe_stats);
 
 		if (iir & (I915_LPE_PIPE_A_INTERRUPT |
 			   I915_LPE_PIPE_B_INTERRUPT))
@@ -1893,7 +1895,8 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
 		if (hotplug_status)
 			i9xx_hpd_irq_handler(dev_priv, hotplug_status);
 
-		valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
+		if (has_pipe_stats)
+			valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
 	} while (0);
 
 	enable_rpm_wakeref_asserts(dev_priv);
@@ -1916,10 +1919,7 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
 
 	master_ctl = I915_READ_FW(GEN8_MASTER_IRQ);
 	do {
-		u32 gt_iir[4], iir;
-		u32 pipe_stats[I915_MAX_PIPES];
-		u32 hotplug_status = 0;
-		bool has_pipe_stats = false;
+		u32 iir;
 
 		/*
 		 * Theory on interrupt generation, based on empirical evidence:
@@ -1935,16 +1935,24 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
 		 * bits this time around.
 		 */
 		if (master_ctl & ~GEN8_MASTER_IRQ_CONTROL) {
+			u32 gt_iir[4];
+
 			I915_WRITE_FW(GEN8_MASTER_IRQ, 0);
 
 			gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir);
 
 			I915_WRITE_FW(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
 			ret = IRQ_HANDLED;
+
+			gen8_gt_irq_handler(dev_priv, master_ctl, gt_iir);
+			master_ctl = 0;
 		}
 
 		iir = I915_READ_FW(VLV_IIR);
 		if (iir) {
+			u32 pipe_stats[I915_MAX_PIPES];
+			u32 hotplug_status = 0;
+			bool has_pipe_stats = false;
 			u32 ier;
 
 			ier = I915_READ_FW(VLV_IER);
@@ -1970,17 +1978,15 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
 			I915_WRITE_FW(VLV_IIR, iir);
 			I915_WRITE_FW(VLV_IER, ier);
 			ret = IRQ_HANDLED;
-		}
-
-		gen8_gt_irq_handler(dev_priv, master_ctl, gt_iir);
 
-		if (hotplug_status)
-			i9xx_hpd_irq_handler(dev_priv, hotplug_status);
+			if (hotplug_status)
+				i9xx_hpd_irq_handler(dev_priv, hotplug_status);
 
-		if (has_pipe_stats)
-			valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
+			if (has_pipe_stats)
+				valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
 
-		master_ctl = I915_READ_FW(GEN8_MASTER_IRQ);
+			master_ctl = I915_READ_FW(GEN8_MASTER_IRQ);
+		}
 	} while (master_ctl & ~GEN8_MASTER_IRQ_CONTROL);
 
 	enable_rpm_wakeref_asserts(dev_priv);
-- 
2.14.1