✗ Fi.CI.BAT: failure for series starting with [01/54] drm/i915: Check whitelist registers across resets

[Patchwork]

== Series Details ==

Series: series starting with [01/54] drm/i915: Check whitelist registers across resets
URL   : https://patchwork.freedesktop.org/series/41678/
State : failure

== Summary ==

= CI Bug Log - changes from CI_DRM_4053 -> Trybot_2041 =

== Summary - FAILURE ==

  Serious unknown changes coming with Trybot_2041 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Trybot_2041, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/41678/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Trybot_2041:

  === IGT changes ===

    ==== Possible regressions ====

    igt at drv_module_reload@basic-reload:
      fi-bsw-n3050:       PASS -> DMESG-FAIL

    
    ==== Warnings ====

    igt at gem_ctx_create@basic:
      fi-elk-e7500:       SKIP -> PASS +6

    igt at gem_ctx_exec@basic:
      fi-ilk-650:         SKIP -> PASS +6
      fi-bwr-2160:        SKIP -> PASS +6

    
== Known issues ==

  Here are the changes found in Trybot_2041 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt at gem_mmap_gtt@basic-small-bo-tiledx:
      fi-gdg-551:         PASS -> FAIL (fdo#102575)

    
  fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575


== Participating hosts (35 -> 33) ==

  Missing    (2): fi-ilk-m540 fi-skl-6700hq 


== Build changes ==

    * Linux: CI_DRM_4053 -> Trybot_2041

  CI_DRM_4053: e2599f775a9c1c27f702e90e6432e555764edcd8 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4429: 80e4910581c7310258375a003a5de9a57ed24546 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Trybot_2041: 9de11c2ade38f96f25d7d31c2a2c942235980f54 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4429: 93b35926a150e318439d2505901288594b3548f5 @ git://anongit.freedesktop.org/piglit


== Linux commits ==

9de11c2ade38 drm/i915: Support per-context user requests for GPU frequency control
a71d107ffa39 drm/i915: Remove unwarranted clamping for hsw/bdw
7771f0a672a1 drm/i915,intel_ips: Enable GPU wait-boosting with IPS
a17f83e499cb drm/i915: Pull IPS into GT power management
d9f985f46da8 drm/i915: Rename rps min/max frequencies
2eab6000c12c drm/i915: Refactor frequency bounds computation
c6036a13eca9 drm/i915: Simplify rc6/rps enabling
f2bf45b75ee1 drm/i915: Enabling rc6 and rps have different requirements, so separate them
be9f31335e3f drm/i915: Split control of rps and rc6
3bd4ae5aa3c6 drm/i915: Reorder GT interface code
c7d48f8064da drm/i915: Remove defunct intel_suspend_gt_powersave()
1488641f7634 drm/i915: Track HAS_RPS alongside HAS_RC6 in the device info
966ddac0db3d drm/i915: Move all the RPS irq handlers to intel_gt_pm
1cd00eb9a2d4 drm/i915: Move rps worker to intel_gt_pm.c
9db48d1d9525 drm/i915: Split GT powermanagement functions to intel_gt_pm.c
c3c3ce74f94c drm/i915: Remove obsolete min/max freq setters from debugfs
9a883af57afc drm/i915: Enable render context support for gen4 (Broadwater to Cantiga)
47c52a87f90b drm/i915: Enable render context support for Ironlake (gen5)
9bfbe5652513 drm/i915: Generalize i915_gem_sanitize() to reset contexts
b8cdd9a282c5 drm/i915: Record logical context support in driver caps
b241890b04a2 drm/i915: Mark up Ironlake ips with rpm wakerefs
5415e477d210 drm/i915: Move sandybride pcode access to intel_sideband.c
3647ac2f5cb3 drm/i915: Merge sandybridge_pcode_(read|write)
9be425dfaf94 drm/i915: Merge sbi read/write into a single accessor
6c58189158d9 drm/i915: Separate sideband declarations to intel_sideband.h
9b5d786dc211 drm/i915: Replace pcu_lock with sb_lock
d9ef8081300e Revert "drm/i915: Avoid tweaking evaluation thresholds on Baytrail v3"
fb73819236b9 drm/i915: Reduce RPS update frequency on Valleyview/Cherryview
bc1913027410 drm/i915: Lift sideband locking for vlv_punit_(read|write)
69264f15550f drm/i915: Lift acquiring the vlv punit magic to a common sb-get
10dde7210ff5 drm/i915: Disable preemption and sleeping while using the punit sideband
18f570918adf drm/i915: Request driver probe from an async task
4c99638504f0 drm/i915/execlists: Delay updating ring register state after resume
c0fca7547ffc sigh
c25aed6b8490 drm/i915: Allow user control over preempt timeout on their important context
bef2021e7819 drm/i915: Use a preemption timeout to enforce interactivity
1f235f668ead drm/i915/preemption: Select timeout when scheduling
e6318f5e7436 drm/i915/execlists: Try preempt-reset from hardirq timer context
e97b74e3ada2 drm/i915/execlists: Force preemption via reset on timeout
235ab1ab5315 drm/i915: Compile out engine debug for release
b8dcb71937fd drm/i915: Allow init_breadcrumbs to be used from irq context
4d413733eaed drm/i915/guc: Make submission tasklet hardirq safe
3243791f7c3c drm/i915/execlists: Make submission tasklet hardirq safe
da5523ad5e84 drm/i915: Be irqsafe inside reset
09d5e787aff2 drm/i915: Stop parking the signaler around reset
829ddd2a72f9 drm/i915: Combine tasklet_kill and tasklet_disable
10f3069c0ebf drm/i915/breadcrumbs: Keep the fake irq armed across reset
3181f7762bf6 drm/i915/execlists: Flush pending preemption events during reset
05b58e3c072a drm/i915: Split execlists/guc reset preparations
d8f459ee220b drm/i915: Move engine reset prepare/finish to backends
67042fda85c4 drm/i915/execlists: Refactor out complete_preempt_context()
1045c26904c4 drm/i915/selftests: Wait for idle between idle resets as well
459ebfcc0e5a drm/i915: Pack params to engine->schedule() into a struct
d8a3ca51b015 drm/i915: Check whitelist registers across resets

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_2041/issues.html