[PATCH 06/10] drm/i915: make GEN7 intel GPU series configurable
Andi Shyti
andi.shyti at intel.com
Wed Sep 12 13:18:17 UTC 2018
GEN7 consists of
Ivy Bridge
Valley View
Haswell
GPUs.
Haswell is defined as 7.5.
A GEN8 define has been added because of GEN8 dependency from
GEN75 (which depends from GEN7). Without the GEN8 define, the
compile issues an error. This will be fixed in the next patch.
Signed-off-by: Andi Shyti <andi.shyti at intel.com>
---
drivers/gpu/drm/i915/Kconfig.sel | 44 ++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/i915_drv.h | 8 +++---
drivers/gpu/drm/i915/i915_pci.c | 18 +++++++++++++
3 files changed, 66 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/Kconfig.sel b/drivers/gpu/drm/i915/Kconfig.sel
index fca3efd80fa3..ed8949010399 100644
--- a/drivers/gpu/drm/i915/Kconfig.sel
+++ b/drivers/gpu/drm/i915/Kconfig.sel
@@ -150,3 +150,47 @@ config DRM_INTEL_SANDYBRIDGE
select DRM_INTEL_GEN6
help
Choose this option if you have a Sandy Bridge gpu
+
+comment "Intel GEN7"
+
+config DRM_INTEL_GEN7
+ bool
+
+config DRM_INTEL_IVYBRIDGE
+ bool "Intel Ivy Bridge GPU"
+ default y
+ depends on DRM_I915
+ select DRM_INTEL_GEN7
+ help
+ Choose this option if you have an Ivy Bridge gpu
+
+config DRM_INTEL_VALLEYVIEW
+ bool "Intel Valley View GPU"
+ default y
+ depends on DRM_I915
+ select DRM_INTEL_GEN7
+ help
+ Choose this option if you have a Valley View gpu
+
+comment "Intel GEN7.5"
+
+config DRM_INTEL_GEN75
+ bool
+ select DRM_INTEL_GEN7
+
+config DRM_INTEL_HASWELL
+ bool "Intel Haswell GPU"
+ default y
+ depends on DRM_I915
+ select DRM_INTEL_GEN75
+ help
+ Choose this option if you have a Haswell gpu
+
+# this is temporary to avoid GEN8 compilation error
+
+comment "Temporary GEN8 definition"
+
+config DRM_INTEL_GEN8
+ bool
+ default y
+ select DRM_INTEL_GEN75
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3637e0ab2268..eb3cd3d79231 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2396,12 +2396,12 @@ intel_info(const struct drm_i915_private *dev_priv)
#define IS_PINEVIEW(dev_priv) IS_SELECTED_PLATFORM(dev_priv, INTEL_PINEVIEW)
#define IS_G33(dev_priv) IS_SELECTED_PLATFORM(dev_priv, INTEL_G33)
#define IS_IRONLAKE_M(dev_priv) IS_SELECTED_ID(dev_priv, INTEL_IRONLAKE, 0x0046)
-#define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
+#define IS_IVYBRIDGE(dev_priv) IS_SELECTED_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
#define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \
(dev_priv)->info.gt == 1)
-#define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
+#define IS_VALLEYVIEW(dev_priv) IS_SELECTED_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
#define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
-#define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL)
+#define IS_HASWELL(dev_priv) IS_SELECTED_PLATFORM(dev_priv, INTEL_HASWELL)
#define IS_BROADWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROADWELL)
#define IS_SKYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
#define IS_BROXTON(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROXTON)
@@ -2523,7 +2523,6 @@ intel_info(const struct drm_i915_private *dev_priv)
* have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
* chips, etc.).
*/
-#define IS_GEN7(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(6)))
#define IS_GEN8(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(7)))
#define IS_GEN9(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(8)))
#define IS_GEN10(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(9)))
@@ -2536,6 +2535,7 @@ intel_info(const struct drm_i915_private *dev_priv)
#define IS_GEN4(dev_priv) __IS_GEN_X(4, dev_priv)
#define IS_GEN5(dev_priv) __IS_GEN_X(5, dev_priv)
#define IS_GEN6(dev_priv) __IS_GEN_X(6, dev_priv)
+#define IS_GEN7(dev_priv) __IS_GEN_X(7, dev_priv)
#define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
#define IS_GEN9_LP(dev_priv) (IS_GEN9(dev_priv) && IS_LP(dev_priv))
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index c169de9fcf72..4c385f04f997 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -327,6 +327,7 @@ static const struct intel_device_info intel_sandybridge_m_gt2_info = {
};
#endif
+#ifdef CONFIG_DRM_INTEL_GEN7
#define GEN7_FEATURES \
GEN(7), \
.num_pipes = 3, \
@@ -342,7 +343,9 @@ static const struct intel_device_info intel_sandybridge_m_gt2_info = {
GEN_DEFAULT_PIPEOFFSETS, \
GEN_DEFAULT_PAGE_SIZES, \
IVB_CURSOR_OFFSETS
+#endif
+#ifdef CONDFIG_DRM_INTEL_IVYBRIDGE
#define IVB_D_PLATFORM \
GEN7_FEATURES, \
PLATFORM(INTEL_IVYBRIDGE), \
@@ -381,7 +384,9 @@ static const struct intel_device_info intel_ivybridge_q_info = {
.num_pipes = 0, /* legal, last one wins */
.has_l3_dpf = 1,
};
+#endif
+#ifdef CONFIG_DRM_INTEL_VALLEYVIEW
static const struct intel_device_info intel_valleyview_info = {
PLATFORM(INTEL_VALLEYVIEW),
GEN(7),
@@ -401,7 +406,9 @@ static const struct intel_device_info intel_valleyview_info = {
GEN_DEFAULT_PIPEOFFSETS,
CURSOR_OFFSETS
};
+#endif
+#ifdef CONFIG_DRM_INTEL_GEN75
#define G75_FEATURES \
GEN7_FEATURES, \
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
@@ -411,7 +418,9 @@ static const struct intel_device_info intel_valleyview_info = {
.has_dp_mst = 1, \
.has_rc6p = 0 /* RC6p removed-by HSW */, \
.has_runtime_pm = 1
+#endif
+#ifdef CONFIG_DRM_INTEL_HASWELL
#define HSW_PLATFORM \
G75_FEATURES, \
PLATFORM(INTEL_HASWELL), \
@@ -431,7 +440,9 @@ static const struct intel_device_info intel_haswell_gt3_info = {
HSW_PLATFORM,
.gt = 3,
};
+#endif
+#ifdef CONFIG_DRM_INTEL_GEN8
#define GEN8_FEATURES \
G75_FEATURES, \
GEN(8), \
@@ -446,6 +457,7 @@ static const struct intel_device_info intel_haswell_gt3_info = {
#define BDW_PLATFORM \
GEN8_FEATURES, \
PLATFORM(INTEL_BROADWELL)
+#endif
static const struct intel_device_info intel_broadwell_gt1_info = {
BDW_PLATFORM,
@@ -711,15 +723,21 @@ static const struct pci_device_id pciidlist[] = {
INTEL_SNB_M_GT1_IDS(&intel_sandybridge_m_gt1_info),
INTEL_SNB_M_GT2_IDS(&intel_sandybridge_m_gt2_info),
#endif
+#ifdef CONDFIG_DRM_INTEL_IVYBRIDGE
INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */
INTEL_IVB_M_GT1_IDS(&intel_ivybridge_m_gt1_info),
INTEL_IVB_M_GT2_IDS(&intel_ivybridge_m_gt2_info),
INTEL_IVB_D_GT1_IDS(&intel_ivybridge_d_gt1_info),
INTEL_IVB_D_GT2_IDS(&intel_ivybridge_d_gt2_info),
+#endif
+#ifdef CONFIG_DRM_INTEL_HASWELL
INTEL_HSW_GT1_IDS(&intel_haswell_gt1_info),
INTEL_HSW_GT2_IDS(&intel_haswell_gt2_info),
INTEL_HSW_GT3_IDS(&intel_haswell_gt3_info),
+#endif
+#ifdef CONFIG_DRM_INTEL_VALLEYVIEW
INTEL_VLV_IDS(&intel_valleyview_info),
+#endif
INTEL_BDW_GT1_IDS(&intel_broadwell_gt1_info),
INTEL_BDW_GT2_IDS(&intel_broadwell_gt2_info),
INTEL_BDW_GT3_IDS(&intel_broadwell_gt3_info),
--
2.19.0
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