[PATCH 4/6] drm/i915/psr: Implement PSR workaround

[José Roberto de Souza]

WA 1110 fix some missing flips when FBC and PSR is enabled.

BSpec: 21664
Signed-off-by: José Roberto de Souza <jose.souza at intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 9 +++++++++
 drivers/gpu/drm/i915/i915_reg.h          | 1 +
 2 files changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 51d8a3231284..13218eaedd9a 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -764,6 +764,15 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
 		I915_WRITE(reg, chicken);
 	}
 
+	/* WA1110 */
+	if (IS_GEN(dev_priv, 9)) {
+		i915_reg_t reg = CHICKEN_TRANS(cpu_transcoder);
+		u32 chicken = I915_READ(reg);
+
+		chicken |= VBLANK_UNMASKED_PSR;
+		I915_WRITE(reg, chicken);
+	}
+
 	/*
 	 * Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD also
 	 * mask LPSP to avoid dependency on other drivers that might block
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 53c280c4e741..b2e0e8c27969 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7715,6 +7715,7 @@ enum {
 					    [TRANSCODER_B] = _CHICKEN_TRANS_B, \
 					    [TRANSCODER_C] = _CHICKEN_TRANS_C, \
 					    [TRANSCODER_D] = _CHICKEN_TRANS_D))
+#define  VBLANK_UNMASKED_PSR		(1 << 30) /* SKL+ */
 #define  VSC_DATA_SEL_SOFTWARE_CONTROL	(1 << 25) /* GLK and CNL+ */
 #define  DDI_TRAINING_OVERRIDE_ENABLE	(1 << 19)
 #define  DDI_TRAINING_OVERRIDE_VALUE	(1 << 18)
-- 
2.23.0