✓ Fi.CI.BAT: success for series starting with [01/64] drm/i915: Use cmpxchg64 for 32b compatilibity

Tue Dec 22 23:48:50 UTC 2020

== Series Details ==

Series: series starting with [01/64] drm/i915: Use cmpxchg64 for 32b compatilibity
URL   : https://patchwork.freedesktop.org/series/85168/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9514 -> Trybot_7357
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_7357/index.html

New tests
---------

  New tests have been introduced between CI_DRM_9514 and Trybot_7357:

### New IGT tests (1) ###

  * igt at i915_selftest@live at scheduler:
    - Statuses : 35 pass(s)
    - Exec time: [0.56, 9.23] s

Known issues
------------

  Here are the changes found in Trybot_7357 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt at gem_basic@create-fd-close:
    - fi-tgl-y:           [PASS][1] -> [DMESG-WARN][2] ([i915#402]) +2 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9514/fi-tgl-y/igt@gem_basic@create-fd-close.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_7357/fi-tgl-y/igt@gem_basic@create-fd-close.html

#### Possible fixes ####

  * igt at i915_selftest@live at gt_heartbeat:
    - fi-kbl-soraka:      [DMESG-FAIL][3] ([i915#2291] / [i915#541]) -> [PASS][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9514/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_7357/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html

  * igt at prime_self_import@basic-with_two_bos:
    - fi-tgl-y:           [DMESG-WARN][5] ([i915#402]) -> [PASS][6] +1 similar issue
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9514/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_7357/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html

  [i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
  [i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541

Participating hosts (43 -> 38)
------------------------------

  Missing    (5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus 

Build changes
-------------

  * Linux: CI_DRM_9514 -> Trybot_7357

  CI-20190529: 20190529
  CI_DRM_9514: 5944be99a80f5839401cfef97be6177b38fda6e9 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5916: 2100c6efd2de767a876977ae1a8a6366e4beb643 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Trybot_7357: 0b5a90545bbf9f345f3e52b2f7b394f0c01eb76f @ git://anongit.freedesktop.org/gfx-ci/linux

== Linux commits ==

0b5a90545bbf rq
25f1349085c9 drm/i915/gt: Enable ring scheduling for gen6/7
7f00ce083699 drm/i915/gt: Implement ring scheduler for gen6/7
677ff2d74cd2 drm/i915/gt: Enable busy-stats for ring-scheduler
2bfc49be2df0 drm/i915/gt: Infrastructure for ring scheduling
e9e69b980f32 drm/i915/gt: Use client timeline address for seqno writes
9113e0df1a20 drm/i915/gt: Support creation of 'internal' rings
30a7693ba3b1 drm/i915/gt: Couple tasklet scheduling for all CS interrupts
2a8af28761bb Restore "drm/i915: drop engine_pin/unpin_breadcrumbs_irq"
3b92cef460c3 drm/i915/gt: Use ppHWSP for unshared non-semaphore related timelines
491b77dc813e drm/i915/selftests: Exercise relative timeline modes
b1fdd61898fb drm/i915/gt: Use indices for writing into relative timelines
96b604f81d21 drm/i915/gt: Add timeline "mode"
819fcef16cec drm/i915/gt: Track timeline GGTT offset separately from subpage offset
8bfff60981ef drm/i915/gt: Wrap intel_timeline.has_initial_breadcrumb
d2c17417f5ee drm/i915: Bump default timeslicing quantum to 5ms
0b7ab04db797 drm/i915: Move saturated workload detection back to the context
f85efecf221f drm/i915/gt: Support virtual engine queues
a30ee6d84f38 drm/i915/gt: Skip over completed active execlists, again
82c9782685d9 drm/i915: Extend the priority boosting for the display with a deadline
80958afac059 drm/i915/gt: Specify a deadline for the heartbeat
168b8285c665 drm/i915: Fair low-latency scheduling
bbaba7ac4409 drm/i915: Wrap cmpxchg64 with try_cmpxchg64() helper
4758c8524ede drm/i915: Replace priolist rbtree with a skiplist
72db8cf1bcb6 drm/i915: Move tasklet from execlists to sched
f6ddf3d1fa3d drm/i915: Move scheduler queue
8899b601fecd drm/i915: Move common active lists from engine to i915_scheduler
ea5a37103bfc drm/i915: Fix the iterative dfs for defering requests
86c52df4c88c drm/i915: Extract the ability to defer and rerun a request later
f951a567e344 drm/i915: Extract request suspension from the execlists backend
55d67306bacb drm/i915: Extract request rewinding from execlists
50167d3df5bb drm/i915: Extract request submission from execlists
e826352fe530 drm/i915: Improve DFS for priority inheritance
468ef287489c drm/i915/selftests: Exercise priority inheritance around an engine loop
d95bb1bc57ae drm/i915/selftests: Measure set-priority duration
b14b646b9959 drm/i915: Restructure priority inheritance
c7c6db08f35a drm/i915: Teach the i915_dependency to use a double-lock
a1d9eb321458 drm/i915: Replace engine->schedule() with a known request operation
5cb8e10ee155 drm/i915: Remove I915_USER_PRIORITY_SHIFT
dfe71c6332c1 drm/i915: Strip out internal priorities
6fce83742c99 drm/i915/gt: Remove timeslice suppression
c63bec9e7b98 drm/i915/gt: Do not suspend bonded requests if one hangs
dcc1676f5dd5 drm/i915/gt: Refactor heartbeat request construction and submission
8da2f8782c96 drm/i915/gt: Convert stats.active to plain unsigned int
f0f98148d763 drm/i915/gt: Extract busy-stats for ring-scheduler
d5a6a957ddf6 drm/i915/gt: Drop atomic for engine->fw_active tracking
24e8df28b885 drm/i915: Reduce test_and_set_bit to set_bit in i915_request_submit()
26d51d99a770 drm/i915/gem: Reduce ctx->engines_mutex for get_engines()
3e53b83f63e2 drm/i915/gem: Reduce ctx->engine_mutex for reading the clone source
b4372fd04dea drm/i915: Drop i915_request.lock requirement for intel_rps_boost()
43a2ac0063cf drm/i915: Drop i915_request.lock serialisation around await_start
077814f26c43 drm/i915/gt: Consolidate the CS timestamp clocks
77d1994044fe drm/i915/selftests: Confirm CS_TIMESTAMP / CTX_TIMESTAMP share a clock
0e9f0c99169b drm/i915/gt: ce->inflight updates are now serialised
4c4b45274593 drm/i915/gt: Simplify virtual engine handling for execlists_hold()
0e20908724ee drm/i915/gt: Resubmit the virtual engine on schedule-out
d9bb1cb51f18 drm/i915/gt: Shrink the critical section for irq signaling
a20f2a57a6e5 drm/i915/gt: Remove virtual breadcrumb before transfer
5856be1d39dc drm/i915/gt: Defer schedule_out until after the next dequeue
b71597005343 drm/i915/gt: Decouple inflight virtual engines
232b5585ece9 drm/i915/gt: Use virtual_engine during execlists_dequeue
761ea109e69a drm/i915/gt: Replace direct submit with direct call to tasklet
3148e41f2de8 drm/i915/uc: Squelch load failure error message
2024da36ffda drm/i915: Use cmpxchg64 for 32b compatilibity

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_7357/index.html
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