[PATCH i-g-t 1/3] i915/gem_exec_hostile:
Chris Wilson
chris at chris-wilson.co.uk
Thu Jul 23 11:20:32 UTC 2020
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
---
tests/Makefile.sources | 3 +
tests/i915/gem_exec_hostile.c | 323 ++++++++++++++++++++++++++++++++++
tests/meson.build | 1 +
3 files changed, 327 insertions(+)
create mode 100644 tests/i915/gem_exec_hostile.c
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index 0653c3d35..218305b02 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -239,6 +239,9 @@ gem_exec_flush_SOURCES = i915/gem_exec_flush.c
TESTS_progs += gem_exec_gttfill
gem_exec_gttfill_SOURCES = i915/gem_exec_gttfill.c
+TESTS_progs += gem_exec_hostile
+gem_exec_hostile_SOURCES = i915/gem_exec_hostile.c
+
TESTS_progs += gem_exec_latency
gem_exec_latency_SOURCES = i915/gem_exec_latency.c
diff --git a/tests/i915/gem_exec_hostile.c b/tests/i915/gem_exec_hostile.c
new file mode 100644
index 000000000..743dbe7c3
--- /dev/null
+++ b/tests/i915/gem_exec_hostile.c
@@ -0,0 +1,323 @@
+/*
+ * Copyright © 2020 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include <fcntl.h>
+#include <sys/ioctl.h>
+
+#include "i915/gem.h"
+#include "igt.h"
+
+#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
+
+#define MI_MATH(x) MI_INSTR(0x1a, (x) - 1)
+#define MI_MATH_INSTR(opcode, op1, op2) ((opcode) << 20 | (op1) << 10 | (op2))
+/* Opcodes for MI_MATH_INSTR */
+#define MI_MATH_NOOP MI_MATH_INSTR(0x000, 0x0, 0x0)
+#define MI_MATH_LOAD(op1, op2) MI_MATH_INSTR(0x080, op1, op2)
+#define MI_MATH_LOADINV(op1, op2) MI_MATH_INSTR(0x480, op1, op2)
+#define MI_MATH_LOAD0(op1) MI_MATH_INSTR(0x081, op1)
+#define MI_MATH_LOAD1(op1) MI_MATH_INSTR(0x481, op1)
+#define MI_MATH_ADD MI_MATH_INSTR(0x100, 0x0, 0x0)
+#define MI_MATH_SUB MI_MATH_INSTR(0x101, 0x0, 0x0)
+#define MI_MATH_AND MI_MATH_INSTR(0x102, 0x0, 0x0)
+#define MI_MATH_OR MI_MATH_INSTR(0x103, 0x0, 0x0)
+#define MI_MATH_XOR MI_MATH_INSTR(0x104, 0x0, 0x0)
+#define MI_MATH_STORE(op1, op2) MI_MATH_INSTR(0x180, op1, op2)
+#define MI_MATH_STOREINV(op1, op2) MI_MATH_INSTR(0x580, op1, op2)
+/* Registers used as operands in MI_MATH_INSTR */
+#define MI_MATH_REG(x) (x)
+#define MI_MATH_REG_SRCA 0x20
+#define MI_MATH_REG_SRCB 0x21
+#define MI_MATH_REG_ACCU 0x31
+#define MI_MATH_REG_ZF 0x32
+#define MI_MATH_REG_CF 0x33
+
+#define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 1)
+
+static unsigned int offset_in_page(void *addr)
+{
+ return (uintptr_t)addr & 4095;
+}
+
+static uint64_t div64_u64_round_up(uint64_t x, uint64_t y)
+{
+ return (x + y - 1) / y;
+}
+
+static int read_timestamp_frequency(int i915)
+{
+ int value = 0;
+ drm_i915_getparam_t gp = {
+ .value = &value,
+ .param = I915_PARAM_CS_TIMESTAMP_FREQUENCY,
+ };
+ ioctl(i915, DRM_IOCTL_I915_GETPARAM, &gp);
+ return value;
+}
+
+static uint64_t ns_to_ticks(int i915, uint64_t ns)
+{
+ return div64_u64_round_up(ns * read_timestamp_frequency(i915),
+ NSEC_PER_SEC);
+}
+
+static uint32_t __batch_create(int i915, uint32_t offset)
+{
+ const uint32_t bbe = MI_BATCH_BUFFER_END;
+ uint32_t handle;
+
+ handle = gem_create(i915, ALIGN(offset + 4, 4096));
+ gem_write(i915, handle, offset, &bbe, sizeof(bbe));
+
+ return handle;
+}
+
+static uint32_t batch_create(int i915)
+{
+ return __batch_create(i915, 0);
+}
+
+static void delay(int i915,
+ const struct intel_execution_engine2 *e,
+ uint32_t handle,
+ uint64_t addr,
+ uint64_t ns)
+{
+ const int use_64b = intel_gen(intel_get_drm_devid(i915)) >= 8;
+ const uint32_t base = gem_engine_mmio_base(i915, e->name);
+#define CS_GPR(x) (base + 0x600 + 8 * (x))
+#define RUNTIME (base + 0x3a8)
+ enum { START_TS, NOW_TS };
+ uint32_t *map, *cs, *jmp;
+
+ igt_require(base);
+
+ /* Loop until CTX_TIMESTAMP - initial > @ns */
+
+ cs = map = gem_mmap__device_coherent(i915, handle, 0, 4096, PROT_WRITE);
+
+ *cs++ = MI_LOAD_REGISTER_IMM;
+ *cs++ = CS_GPR(START_TS) + 4;
+ *cs++ = 0;
+ *cs++ = MI_LOAD_REGISTER_REG;
+ *cs++ = RUNTIME;
+ *cs++ = CS_GPR(START_TS);
+
+ while (offset_in_page(cs) & 63)
+ *cs++ = 0;
+ jmp = cs;
+
+ *cs++ = 0x5 << 23; /* MI_ARB_CHECK */
+
+ *cs++ = MI_LOAD_REGISTER_IMM;
+ *cs++ = CS_GPR(NOW_TS) + 4;
+ *cs++ = 0;
+ *cs++ = MI_LOAD_REGISTER_REG;
+ *cs++ = RUNTIME;
+ *cs++ = CS_GPR(NOW_TS);
+
+ /* delta = now - start; inverted to match COND_BBE */
+ *cs++ = MI_MATH(4);
+ *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCA, MI_MATH_REG(NOW_TS));
+ *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCB, MI_MATH_REG(START_TS));
+ *cs++ = MI_MATH_SUB;
+ *cs++ = MI_MATH_STOREINV(MI_MATH_REG(NOW_TS), MI_MATH_REG_ACCU);
+
+ /* Save delta for reading by COND_BBE */
+ *cs++ = 0x24 << 23 | (1 + use_64b); /* SRM */
+ *cs++ = CS_GPR(NOW_TS);
+ *cs++ = addr + 4000;
+ *cs++ = addr >> 32;
+
+ /* Delay between SRM and COND_BBE to post the writes */
+ for (int n = 0; n < 8; n++) {
+ *cs++ = MI_STORE_DWORD_IMM;
+ if (use_64b) {
+ *cs++ = addr + 4064;
+ *cs++ = addr >> 32;
+ } else {
+ *cs++ = 0;
+ *cs++ = addr + 4064;
+ }
+ *cs++ = 0;
+ }
+
+ /* Break if delta > ns */
+ *cs++ = MI_COND_BATCH_BUFFER_END | MI_DO_COMPARE | (1 + use_64b);
+ *cs++ = ~ns_to_ticks(i915, ns);
+ *cs++ = addr + 4000;
+ *cs++ = addr >> 32;
+
+ /* Otherwise back to recalculating delta */
+ *cs++ = MI_BATCH_BUFFER_START | 1 << 8 | use_64b;
+ *cs++ = addr + offset_in_page(jmp);
+ *cs++ = addr >> 32;
+
+ munmap(map, 4096);
+}
+
+static struct drm_i915_gem_exec_object2
+delay_create(int i915, uint32_t ctx,
+ const struct intel_execution_engine2 *e,
+ uint64_t target_ns)
+{
+ struct drm_i915_gem_exec_object2 obj = {
+ .handle = batch_create(i915),
+ .flags = EXEC_OBJECT_SUPPORTS_48B_ADDRESS,
+ };
+ struct drm_i915_gem_execbuffer2 execbuf = {
+ .buffers_ptr = to_user_pointer(&obj),
+ .buffer_count = 1,
+ .rsvd1 = ctx,
+ .flags = e->flags,
+ };
+
+ obj.offset = obj.handle << 12;
+ gem_execbuf(i915, &execbuf);
+ gem_sync(i915, obj.handle);
+
+ delay(i915, e, obj.handle, obj.offset, target_ns);
+
+ obj.flags |= EXEC_OBJECT_PINNED;
+ return obj;
+}
+
+static uint32_t vm_clone(int i915)
+{
+ uint32_t ctx = 0;
+ __gem_context_clone(i915, 0,
+ I915_CONTEXT_CLONE_VM |
+ I915_CONTEXT_CLONE_ENGINES,
+ I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE,
+ &ctx);
+ return ctx;
+}
+
+static int __execbuf(int i915, struct drm_i915_gem_execbuffer2 *execbuf)
+{
+ int err;
+
+ err = 0;
+ if (ioctl(i915, DRM_IOCTL_I915_GEM_EXECBUFFER2, execbuf)) {
+ err = -errno;
+ igt_assume(err);
+ }
+
+ errno = 0;
+ return err;
+}
+
+static void far_fence(int i915)
+{
+ const int ncpus = sysconf(_SC_NPROCESSORS_ONLN);
+ const struct intel_execution_engine2 *e;
+ struct drm_i915_gem_exec_object2 obj[64];
+ unsigned long *counters, contexts, count;
+ uint32_t handle = gem_create(i915, 4096);
+ struct timespec tv;
+
+ counters = mmap(NULL, 4096, PROT_WRITE, MAP_SHARED | MAP_ANON, -1, 0);
+ igt_assert(counters != MAP_FAILED);
+
+ __for_each_physical_engine(i915, e)
+ obj[e->flags] = delay_create(i915, 0, e, NSEC_PER_SEC / 250);
+
+ fcntl(i915, F_SETFL, fcntl(i915, F_GETFL) | O_NONBLOCK);
+ igt_fork(child, ncpus) {
+ struct drm_i915_gem_exec_object2 batch[2] = {
+ {
+ .handle = batch_create(i915),
+ .flags = EXEC_OBJECT_WRITE,
+ }
+ };
+ struct drm_i915_gem_execbuffer2 execbuf = {
+ .buffers_ptr = to_user_pointer(batch),
+ .buffer_count = 2,
+ };
+
+ count = 0;
+ contexts = 0;
+
+ //igt_until_timeout(5) {
+ for (;;) {
+ execbuf.rsvd1 = vm_clone(i915);
+ if (!execbuf.rsvd1)
+ break;
+
+ __for_each_physical_engine(i915, e) {
+ batch[1] = obj[e->flags];
+ execbuf.flags = e->flags;
+
+ while (__execbuf(i915, &execbuf) == 0)
+ count++;
+ }
+
+ gem_context_destroy(i915, execbuf.rsvd1);
+ contexts++;
+ }
+ counters[child * 2 + 0] = contexts;
+ counters[child * 2 + 1] = count;
+
+ execbuf.rsvd1 = 0;
+ batch[1] = batch[0];
+ batch[0].handle = handle;
+ batch[1].flags &= ~EXEC_OBJECT_WRITE;
+ gem_execbuf(i915, &execbuf);
+ }
+ igt_waitchildren();
+
+ __for_each_physical_engine(i915, e)
+ gem_close(i915, obj[e->flags].handle);
+
+ count = counters[1];
+ contexts = counters[0];
+ for (int child = 1; child < ncpus; child++) {
+ contexts += counters[child * 2 + 0];
+ count += counters[child * 2 + 1];
+ }
+
+ igt_info("Created %lu across %lu contexts\n", count, contexts);
+ igt_nsec_elapsed(memset(&tv, 0, sizeof(tv)));
+ gem_sync(i915, handle);
+ igt_info("Synchronisation: %.3fms\n", igt_nsec_elapsed(&tv) * 1e-6);
+
+ gem_close(i915, handle);
+}
+
+igt_main
+{
+ int i915 = -1;
+
+ igt_fixture {
+ i915 = drm_open_driver(DRIVER_INTEL);
+ igt_require_gem(i915);
+ }
+
+ igt_subtest("far-fence") {
+ far_fence(i915);
+ }
+
+ igt_fixture {
+ close(i915);
+ }
+}
diff --git a/tests/meson.build b/tests/meson.build
index ca792ed86..20d349d27 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -145,6 +145,7 @@ i915_progs = [
'gem_exec_fence',
'gem_exec_flush',
'gem_exec_gttfill',
+ 'gem_exec_hostile',
'gem_exec_latency',
'gem_exec_lut_handle',
'gem_exec_nop',
--
2.28.0.rc1
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