[PATCH 1/2] wa
Tvrtko Ursulin
tvrtko.ursulin at linux.intel.com
Tue Apr 27 08:37:14 UTC 2021
From: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 85 ++++++++++++++-----
.../gpu/drm/i915/gt/intel_workarounds_types.h | 1 +
2 files changed, 63 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 5a03a76bb9e2..39e649d6e323 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -107,6 +107,8 @@ static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa)
wal->list = list;
}
+printk("_wa_add reg=%x clr=%x set=%x mask=%x\n",
+ addr, wa->clr, wa->set, wa->mask);
while (start < end) {
unsigned int mid = start + (end - start) / 2;
@@ -116,12 +118,31 @@ static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa)
} else if (i915_mmio_reg_offset(wal->list[mid].reg) > addr) {
end = mid;
} else {
+ u32 overlap;
+
wa_ = &wal->list[mid];
+ overlap = wa->clr & wa_->clr;
+ if (overlap) {
+ DRM_WARN("wal-%s/%s reg=%x %s=%x old=%x/%x new=%x/%x\n",
+ wal->name, wal->engine_name, addr,
+ (wa->set & overlap) != (wa_->set & overlap) ? "CONFLICT" : "overlap",
+ overlap, wa_->clr, wa_->set, wa->clr, wa->set);
+ }
+
+ overlap = (wa->mask & wa_->mask) >> 16;
+ if (overlap) {
+ DRM_WARN("wal-%s/%s masked-reg=%x %s=%x old=%x/%x new=%x/%x\n",
+ wal->name, wal->engine_name, addr,
+ (wa->set & overlap) != (wa_->set & overlap) ? "CONFLICT" : "overlap",
+ overlap, wa_->clr, wa_->set, wa->clr, wa->set);
+
+ }
+
if ((wa->clr | wa_->clr) && !(wa->clr & ~wa_->clr)) {
- DRM_ERROR("Discarding overwritten w/a for reg %04x (clear: %08x, set: %08x)\n",
+ DRM_ERROR("Discarding overwritten w/a for reg %04x (clear: %08x, set: %08x) new set: %x\n",
i915_mmio_reg_offset(wa_->reg),
- wa_->clr, wa_->set);
+ wa_->clr, wa_->set, wa_->set & ~wa->clr);
wa_->set &= ~wa->clr;
}
@@ -162,9 +183,23 @@ static void wa_add(struct i915_wa_list *wal, i915_reg_t reg,
_wa_add(wal, &wa);
}
+static void wa_masked_add(struct i915_wa_list *wal, i915_reg_t reg,
+ u32 set, u32 read_mask)
+{
+ struct i915_wa wa = {
+ .reg = reg,
+ .set = set,
+ .read = read_mask,
+ .mask = set & 0xffff0000,
+ };
+
+ _wa_add(wal, &wa);
+}
+
static void
wa_write_clr_set(struct i915_wa_list *wal, i915_reg_t reg, u32 clear, u32 set)
{
+ GEM_WARN_ON(set && !(clear & set));
wa_add(wal, reg, clear, set, clear);
}
@@ -200,20 +235,20 @@ wa_write_clr(struct i915_wa_list *wal, i915_reg_t reg, u32 clr)
static void
wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
{
- wa_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val);
+ wa_masked_add(wal, reg, _MASKED_BIT_ENABLE(val), val);
}
static void
wa_masked_dis(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
{
- wa_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val);
+ wa_masked_add(wal, reg, _MASKED_BIT_DISABLE(val), val);
}
static void
wa_masked_field_set(struct i915_wa_list *wal, i915_reg_t reg,
u32 mask, u32 val)
{
- wa_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask);
+ wa_masked_add(wal, reg, _MASKED_FIELD(mask, val), mask);
}
static void gen6_ctx_workarounds_init(struct intel_engine_cs *engine,
@@ -836,10 +871,10 @@ hsw_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
/* L3 caching of data atomics doesn't work -- disable it. */
wa_write(wal, HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
- wa_add(wal,
- HSW_ROW_CHICKEN3, 0,
- _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE),
- 0 /* XXX does this reg exist? */);
+ wa_masked_add(wal,
+ HSW_ROW_CHICKEN3,
+ _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE),
+ 0 /* XXX does this reg exist? */);
/* WaVSRefCountFullforceMissDisable:hsw */
wa_write_clr(wal, GEN7_FF_THREAD_MODE, GEN7_FF_VS_REF_CNT_FFME);
@@ -1950,10 +1985,11 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
* disable bit, which we don't touch here, but it's good
* to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
*/
- wa_add(wal, GEN7_GT_MODE, 0,
- _MASKED_FIELD(GEN6_WIZ_HASHING_MASK,
- GEN6_WIZ_HASHING_16x4),
- GEN6_WIZ_HASHING_16x4);
+ wa_masked_add(wal,
+ GEN7_GT_MODE,
+ _MASKED_FIELD(GEN6_WIZ_HASHING_MASK,
+ GEN6_WIZ_HASHING_16x4),
+ GEN6_WIZ_HASHING_16x4);
}
if (IS_GEN_RANGE(i915, 6, 7))
@@ -2003,9 +2039,10 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
* disable bit, which we don't touch here, but it's good
* to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
*/
- wa_add(wal,
- GEN6_GT_MODE, 0,
- _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4),
+ wa_masked_add(wal,
+ GEN6_GT_MODE,
+ _MASKED_FIELD(GEN6_WIZ_HASHING_MASK,
+ GEN6_WIZ_HASHING_16x4),
GEN6_WIZ_HASHING_16x4);
/* WaDisable_RenderCache_OperationalFlush:snb */
@@ -2024,10 +2061,11 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
if (IS_GEN_RANGE(i915, 4, 6))
/* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
- wa_add(wal, MI_MODE,
- 0, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH),
- /* XXX bit doesn't stick on Broadwater */
- IS_I965G(i915) ? 0 : VS_TIMER_DISPATCH);
+ wa_masked_add(wal,
+ MI_MODE,
+ _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH),
+ /* XXX bit doesn't stick on Broadwater */
+ IS_I965G(i915) ? 0 : VS_TIMER_DISPATCH);
if (IS_GEN(i915, 4))
/*
@@ -2040,9 +2078,10 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
* they are already accustomed to from before contexts were
* enabled.
*/
- wa_add(wal, ECOSKPD,
- 0, _MASKED_BIT_ENABLE(ECO_CONSTANT_BUFFER_SR_DISABLE),
- 0 /* XXX bit doesn't stick on Broadwater */);
+ wa_masked_add(wal,
+ ECOSKPD,
+ _MASKED_BIT_ENABLE(ECO_CONSTANT_BUFFER_SR_DISABLE),
+ 0 /* XXX bit doesn't stick on Broadwater */);
}
static void
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds_types.h b/drivers/gpu/drm/i915/gt/intel_workarounds_types.h
index c214111ea367..156d14d5d6f4 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds_types.h
@@ -15,6 +15,7 @@ struct i915_wa {
u32 clr;
u32 set;
u32 read;
+ u32 mask;
};
struct i915_wa_list {
--
2.30.2
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