[PATCH 7/8] WIP: drm/i915/display: Allow PSR and seamless DRRS together

[José Roberto de Souza]

There is nothing in specification preventing it at least
in display 9+ specification.
As PSR is only supported in display 9 we can enable both features
together.

This will only bring an actual additional power-savings when
user-space is using seamless mode switch, otherwise at every flip
or frontbuffer write DRRS will go to high refresh mode and will
consume the same as PSR alone.

Just to avoid any pontential issue, here also calling
intel_drrs_invalidate() before intel_psr_invalidate() to not
switch refresh rate in the middle of PSR internal hardware sequences
and also to follow the drrs/psr_flush() order.

TODO: causing sink CRC mismatch when DRRS low mode is on

Signed-off-by: José Roberto de Souza <jose.souza at intel.com>
---
 .../drm/i915/display/intel_display_types.h    |  1 +
 drivers/gpu/drm/i915/display/intel_drrs.c     | 26 ++++++++++---------
 .../gpu/drm/i915/display/intel_frontbuffer.c  |  2 +-
 3 files changed, 16 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index a405f43eee13f..e839b49e99d97 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1317,6 +1317,7 @@ struct intel_crtc {
 		enum transcoder cpu_transcoder;
 		struct intel_link_m_n m_n, m2_n2;
 		bool seamless_mode_switch_enabled;
+		bool psr_enabled;
 	} drrs;
 
 	int scanline_offset;
diff --git a/drivers/gpu/drm/i915/display/intel_drrs.c b/drivers/gpu/drm/i915/display/intel_drrs.c
index fafcb24f3e13a..e6d4433f906f1 100644
--- a/drivers/gpu/drm/i915/display/intel_drrs.c
+++ b/drivers/gpu/drm/i915/display/intel_drrs.c
@@ -68,17 +68,8 @@ static bool can_enable_drrs(struct intel_connector *connector,
 	if (pipe_config->vrr.enable)
 		return false;
 
-	/*
-	 * DRRS and PSR can't be enable together, so giving preference to PSR
-	 * as it allows more power-savings by complete shutting down display,
-	 * so to guarantee this, intel_drrs_compute_config() must be called
-	 * after intel_psr_compute_config().
-	 */
-	if (pipe_config->has_psr)
-		return false;
-
 	return downclock_mode &&
-		intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS;
+	       intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS;
 }
 
 void
@@ -256,6 +247,7 @@ void intel_drrs_activate(const struct intel_crtc_state *crtc_state)
 	crtc->drrs.m2_n2 = crtc_state->dp_m2_n2;
 	crtc->drrs.frontbuffer_bits = intel_drrs_frontbuffer_bits(crtc_state);
 	crtc->drrs.busy_frontbuffer_bits = 0;
+	crtc->drrs.psr_enabled = crtc_state->has_psr;
 
 	intel_drrs_schedule_work(crtc);
 exit:
@@ -323,10 +315,20 @@ static void intel_drrs_downclock_work(struct work_struct *work)
 
 	mutex_lock(&crtc->drrs.mutex);
 
-	if (intel_drrs_is_active(crtc) && !crtc->drrs.busy_frontbuffer_bits &&
-	    !crtc->drrs.seamless_mode_switch_enabled)
+	if (crtc->drrs.seamless_mode_switch_enabled)
+		goto unlock;
+
+	/*
+	 * When PSR is enabled and seamless_mode_switch_enabled not set,
+	 * the DRRS mode switch will only cause display to wake up from DC5/6.
+	 */
+	if (crtc->drrs.psr_enabled)
+		goto unlock;
+
+	if (intel_drrs_is_active(crtc) && !crtc->drrs.busy_frontbuffer_bits)
 		intel_drrs_set_state(crtc, DRRS_REFRESH_RATE_LOW);
 
+unlock:
 	mutex_unlock(&crtc->drrs.mutex);
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_frontbuffer.c b/drivers/gpu/drm/i915/display/intel_frontbuffer.c
index 791248f812aa7..a69c28549b7a4 100644
--- a/drivers/gpu/drm/i915/display/intel_frontbuffer.c
+++ b/drivers/gpu/drm/i915/display/intel_frontbuffer.c
@@ -179,8 +179,8 @@ void __intel_fb_invalidate(struct intel_frontbuffer *front,
 	trace_intel_frontbuffer_invalidate(frontbuffer_bits, origin);
 
 	might_sleep();
-	intel_psr_invalidate(i915, frontbuffer_bits, origin);
 	intel_drrs_invalidate(i915, frontbuffer_bits);
+	intel_psr_invalidate(i915, frontbuffer_bits, origin);
 	intel_fbc_invalidate(i915, frontbuffer_bits, origin);
 }
 
-- 
2.35.1