[PATCH 04/10] drm/i915/dp: Compute output format with/without DSC
Ankit Nautiyal
ankit.k.nautiyal at intel.com
Thu Nov 17 06:59:52 UTC 2022
Currently we compute the output format first and later try DSC if the
bandwidth without compression is not sufficient for that output format.
Since we do not support DSC with YCbCr420 format, this creates problem
for YCbCr420 only modes, that can be still be set if DFP has color
conversion and DSC capabilities.
So compute output format, first without DSC and inturn compute the link
config without DSC. If cannot be supported without DSC, compute the
output format with DSC and continue.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal at intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 73 +++++++++++++++----------
1 file changed, 43 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 3ca944d91811..f19fbe31f8b7 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -849,18 +849,18 @@ dfp_can_convert_from_ycbcr444(struct intel_dp *intel_dp,
static enum intel_output_format
intel_dp_output_format(struct intel_connector *connector,
- enum intel_output_format sink_format)
+ enum intel_output_format sink_format,
+ bool with_dsc)
{
struct intel_dp *intel_dp = intel_attached_dp(connector);
+
/*
- * FIXME: The correct order should have been:
- * First try with with native RGb/YCbCr420 support,
- * if not possible go with RGB and try with DFP color conv.
- * But problem is with case of Native 420 support.
- * Currently we do not support DSC with native 420,
- * but source_can_output(YCbCr420) does not take into account
- * if DSC will be used.
+ * Currently we do not support DSC with native YCbCr420.
+ * So check for native YCbCr420 only when trying without DSC.
*/
+ if ((sink_format != INTEL_OUTPUT_FORMAT_YCBCR420 || !with_dsc) &&
+ (source_can_output(intel_dp, sink_format)))
+ return sink_format;
if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_RGB) &&
dfp_can_convert_from_rgb(intel_dp, sink_format))
@@ -870,8 +870,6 @@ intel_dp_output_format(struct intel_connector *connector,
dfp_can_convert_from_ycbcr444(intel_dp, sink_format))
return INTEL_OUTPUT_FORMAT_YCBCR444;
- if (source_can_output(intel_dp, sink_format))
- return sink_format;
return INTEL_OUTPUT_FORMAT_RGB;
}
@@ -909,7 +907,7 @@ intel_dp_mode_min_output_bpp(struct intel_connector *connector,
else
sink_format = INTEL_OUTPUT_FORMAT_RGB;
- output_format = intel_dp_output_format(connector, sink_format);
+ output_format = intel_dp_output_format(connector, sink_format, false);
return intel_dp_output_bpp(output_format, intel_dp_min_bpp(output_format));
}
@@ -1658,7 +1656,8 @@ static int
intel_dp_compute_link_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config,
struct drm_connector_state *conn_state,
- bool respect_downstream_limits)
+ bool respect_downstream_limits,
+ bool with_dsc)
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
@@ -1669,6 +1668,20 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
bool joiner_needs_dsc = false;
int ret;
+ if (intel_dp_need_bigjoiner(intel_dp, adjusted_mode->crtc_hdisplay,
+ adjusted_mode->crtc_clock))
+ pipe_config->bigjoiner_pipes = GENMASK(crtc->pipe + 1, crtc->pipe);
+
+ /*
+ * Pipe joiner needs compression up to display 12 due to bandwidth
+ * limitation. DG2 onwards pipe joiner can be enabled without
+ * compression.
+ */
+ joiner_needs_dsc = DISPLAY_VER(i915) < 13 && pipe_config->bigjoiner_pipes;
+
+ if (joiner_needs_dsc && !with_dsc)
+ return -EINVAL;
+
limits.min_rate = intel_dp_common_rate(intel_dp, 0);
limits.max_rate = intel_dp_max_link_rate(intel_dp);
@@ -1698,23 +1711,15 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
limits.max_lane_count, limits.max_rate,
limits.max_bpp, adjusted_mode->crtc_clock);
- if (intel_dp_need_bigjoiner(intel_dp, adjusted_mode->crtc_hdisplay,
- adjusted_mode->crtc_clock))
- pipe_config->bigjoiner_pipes = GENMASK(crtc->pipe + 1, crtc->pipe);
-
- /*
- * Pipe joiner needs compression up to display 12 due to bandwidth
- * limitation. DG2 onwards pipe joiner can be enabled without
- * compression.
- */
- joiner_needs_dsc = DISPLAY_VER(i915) < 13 && pipe_config->bigjoiner_pipes;
-
/*
* Optimize for slow and wide for everything, because there are some
* eDP 1.3 and 1.4 panels don't work well with fast and narrow.
*/
ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, conn_state, &limits);
+ if (ret && !with_dsc)
+ return -EINVAL;
+
if (ret || joiner_needs_dsc || intel_dp->force_dsc_en) {
drm_dbg_kms(&i915->drm, "Try DSC (fallback=%s, joiner=%s, force=%s)\n",
str_yes_no(ret), str_yes_no(joiner_needs_dsc),
@@ -2050,7 +2055,8 @@ static int
intel_dp_compute_output_format(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state,
struct drm_connector_state *conn_state,
- bool respect_downstream_limits)
+ bool respect_downstream_limits,
+ bool with_dsc)
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
@@ -2072,10 +2078,10 @@ intel_dp_compute_output_format(struct intel_encoder *encoder,
crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB;
}
- crtc_state->output_format = intel_dp_output_format(connector, crtc_state->sink_format);
+ crtc_state->output_format = intel_dp_output_format(connector, crtc_state->sink_format, with_dsc);
ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
- respect_downstream_limits);
+ respect_downstream_limits, with_dsc);
if (ret) {
if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
!drm_mode_is_420_also(info, adjusted_mode))
@@ -2083,9 +2089,9 @@ intel_dp_compute_output_format(struct intel_encoder *encoder,
crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
crtc_state->output_format = intel_dp_output_format(connector,
- crtc_state->sink_format);
+ crtc_state->sink_format, with_dsc);
ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
- respect_downstream_limits);
+ respect_downstream_limits, with_dsc);
}
return ret;
@@ -2132,12 +2138,19 @@ intel_dp_compute_config(struct intel_encoder *encoder,
* Try to respect downstream TMDS clock limits first, if
* that fails assume the user might know something we don't.
*/
- ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, true);
+ ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, true, false);
if (ret)
- ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, false);
+ ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, false, false);
if (ret)
return ret;
+ /* If DSC is supported try with DSC */
+ if (ret && intel_dp_supports_dsc(intel_dp, pipe_config)) {
+ ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, true, true);
+ if (ret)
+ ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, false, true);
+ }
+
if ((intel_dp_is_edp(intel_dp) && fixed_mode) ||
pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
ret = intel_panel_fitting(pipe_config, conn_state);
--
2.25.1
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