[PATCH 1/2] drm/i915/psr: Use flags for PSR mode instead of booleans
Jouni Högander
jouni.hogander at intel.com
Tue Sep 5 09:32:27 UTC 2023
Number of PSR booleans is about to increase. It is not convenient to add
more of these. Also re-using old booleans is making code flows obscure. Due
to this conver existing booleans to flags.
Signed-off-by: Jouni Högander <jouni.hogander at intel.com>
---
.../drm/i915/display/intel_display_types.h | 21 ++--
drivers/gpu/drm/i915/display/intel_psr.c | 112 +++++++++++-------
2 files changed, 79 insertions(+), 54 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index c21064794f32..672ac676fbcb 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1655,6 +1655,12 @@ struct intel_pps {
struct edp_power_seq bios_pps_delays;
};
+enum intel_psr_flags {
+ INTEL_PSR = 1,
+ INTEL_PSR2 = 2,
+ INTEL_PSR2_SELECTIVE_FETCH = 3,
+};
+
struct intel_psr {
/* Mutex for PSR state of the transcoder */
struct mutex lock;
@@ -1667,21 +1673,20 @@ struct intel_psr {
#define I915_PSR_DEBUG_ENABLE_SEL_FETCH 0x4
#define I915_PSR_DEBUG_IRQ 0x10
+
+
u32 debug;
- bool sink_support;
- bool source_support;
- bool enabled;
+ u32 sink_support;
+ u32 source_support;
+ u32 enabled;
bool paused;
enum pipe pipe;
enum transcoder transcoder;
bool active;
struct work_struct work;
unsigned int busy_frontbuffer_bits;
- bool sink_psr2_support;
bool link_standby;
bool colorimetry_support;
- bool psr2_enabled;
- bool psr2_sel_fetch_enabled;
bool psr2_sel_fetch_cff_enabled;
bool req_psr2_sdp_prior_scanline;
u8 sink_sync_latency;
@@ -1980,8 +1985,8 @@ dp_to_lspcon(struct intel_dp *intel_dp)
#define dp_to_i915(__intel_dp) to_i915(dp_to_dig_port(__intel_dp)->base.base.dev)
-#define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \
- (intel_dp)->psr.source_support)
+#define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support & BIT(INTEL_PSR) && \
+ (intel_dp)->psr.source_support & BIT(INTEL_PSR))
static inline bool intel_encoder_can_psr(struct intel_encoder *encoder)
{
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index b9e38acc5132..39c8baf87661 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -84,6 +84,25 @@
* Front buffer modifications do not trigger DC3CO activation on purpose as it
* would bring a lot of complexity and most of the moderns systems will only
* use page flips.
+ *
+ * PSR Flags
+ *
+ * PSR code uses several flags used to indicate sink/source support and what is
+ * being enabled. These flags are defined in as enum intel_psr_flags and
+ * they are representing bit position:
+ * INTEL_PSR
+ * This is main flags indicating sink/source is supporting PSR1. When the flag
+ * is indicating enabled mode and set alone it means PSR1 being
+ * enabled.
+ * INTEL_PSR2
+ * This is indicating sink/source is supporting PSR2 i.e. PSR with selective
+ * updates. It can be set only together with INTEL_PSR flag.
+ * INTEL_PSR2_SELECTIVE_FETCH
+ * This is flags specific to Intel HW. I.e. selective update using selective
+ * fetch and software tracking mechanism. Older platforms were supporting only
+ * hw tracking without selective fetch. Tigerlake supports both but currently
+ * driver is supporting only selective fetch for it. This flag is always set
+ * together with INTEL_PSR2. this is not valid flag for sink support.
*/
/*
@@ -323,12 +342,12 @@ static void psr_irq_control(struct intel_dp *intel_dp)
}
static void psr_event_print(struct drm_i915_private *i915,
- u32 val, bool psr2_enabled)
+ u32 val, u32 enabled)
{
drm_dbg_kms(&i915->drm, "PSR exit events: 0x%x\n", val);
if (val & PSR_EVENT_PSR2_WD_TIMER_EXPIRE)
drm_dbg_kms(&i915->drm, "\tPSR2 watchdog timer expired\n");
- if ((val & PSR_EVENT_PSR2_DISABLED) && psr2_enabled)
+ if ((val & PSR_EVENT_PSR2_DISABLED) && enabled & BIT(INTEL_PSR2))
drm_dbg_kms(&i915->drm, "\tPSR2 disabled\n");
if (val & PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN)
drm_dbg_kms(&i915->drm, "\tSU dirty FIFO underrun\n");
@@ -356,7 +375,7 @@ static void psr_event_print(struct drm_i915_private *i915,
drm_dbg_kms(&i915->drm, "\tVBI enabled\n");
if (val & PSR_EVENT_LPSP_MODE_EXIT)
drm_dbg_kms(&i915->drm, "\tLPSP mode exited\n");
- if ((val & PSR_EVENT_PSR_DISABLE) && !psr2_enabled)
+ if ((val & PSR_EVENT_PSR_DISABLE) && !(enabled & BIT(INTEL_PSR2)))
drm_dbg_kms(&i915->drm, "\tPSR disabled\n");
}
@@ -384,7 +403,7 @@ void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir)
val = intel_de_rmw(dev_priv, PSR_EVENT(cpu_transcoder), 0, 0);
- psr_event_print(dev_priv, val, intel_dp->psr.psr2_enabled);
+ psr_event_print(dev_priv, val, intel_dp->psr.enabled);
}
}
@@ -498,7 +517,7 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
return;
}
- intel_dp->psr.sink_support = true;
+ intel_dp->psr.sink_support |= BIT(INTEL_PSR);
intel_dp->psr.sink_sync_latency =
intel_dp_get_sink_sync_latency(intel_dp);
@@ -519,11 +538,11 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
* Y-coordinate requirement panels we would need to enable
* GTC first.
*/
- intel_dp->psr.sink_psr2_support = y_req && alpm;
+ intel_dp->psr.sink_support |= y_req && alpm ? BIT(INTEL_PSR2) : 0;
drm_dbg_kms(&dev_priv->drm, "PSR2 %ssupported\n",
- intel_dp->psr.sink_psr2_support ? "" : "not ");
+ intel_dp->psr.sink_support & BIT(INTEL_PSR2) ? "" : "not ");
- if (intel_dp->psr.sink_psr2_support) {
+ if (intel_dp->psr.sink_support & BIT(INTEL_PSR2)) {
intel_dp->psr.colorimetry_support =
intel_dp_get_colorimetry_status(intel_dp);
intel_dp_get_su_granularity(intel_dp);
@@ -574,7 +593,7 @@ static void intel_psr_enable_sink(struct intel_dp *intel_dp)
u8 dpcd_val = DP_PSR_ENABLE;
/* Enable ALPM at sink for psr2 */
- if (intel_dp->psr.psr2_enabled) {
+ if (intel_dp->psr.enabled & BIT(INTEL_PSR2)) {
drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG,
DP_ALPM_ENABLE |
DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE);
@@ -782,7 +801,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
if (intel_dp->psr.req_psr2_sdp_prior_scanline)
val |= EDP_PSR2_SU_SDP_SCANLINE;
- if (intel_dp->psr.psr2_sel_fetch_enabled) {
+ if (intel_dp->psr.enabled & BIT(INTEL_PSR2_SELECTIVE_FETCH)) {
u32 tmp;
tmp = intel_de_read(dev_priv, PSR2_MAN_TRK_CTL(cpu_transcoder));
@@ -1071,7 +1090,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay;
int psr_max_h = 0, psr_max_v = 0, max_bpp = 0;
- if (!intel_dp->psr.sink_psr2_support)
+ if (!(intel_dp->psr.sink_support & INTEL_PSR2))
return false;
/* JSL and EHL only supports eDP 1.3 */
@@ -1288,10 +1307,10 @@ void intel_psr_get_config(struct intel_encoder *encoder,
* enabled/disabled because of frontbuffer tracking and others.
*/
pipe_config->has_psr = true;
- pipe_config->has_psr2 = intel_dp->psr.psr2_enabled;
+ pipe_config->has_psr2 = intel_dp->psr.enabled & BIT(INTEL_PSR2);
pipe_config->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
- if (!intel_dp->psr.psr2_enabled)
+ if (!(intel_dp->psr.enabled & BIT(INTEL_PSR2)))
goto unlock;
if (HAS_PSR2_SEL_FETCH(dev_priv)) {
@@ -1325,7 +1344,7 @@ static void intel_psr_activate(struct intel_dp *intel_dp)
lockdep_assert_held(&intel_dp->psr.lock);
/* psr1 and psr2 are mutually exclusive.*/
- if (intel_dp->psr.psr2_enabled)
+ if (intel_dp->psr.enabled & BIT(INTEL_PSR2))
hsw_activate_psr2(intel_dp);
else
hsw_activate_psr1(intel_dp);
@@ -1427,7 +1446,8 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
if (HAS_PSR_HW_TRACKING(dev_priv) && HAS_PSR2_SEL_FETCH(dev_priv))
intel_de_rmw(dev_priv, CHICKEN_PAR1_1, IGNORE_PSR2_HW_TRACKING,
- intel_dp->psr.psr2_sel_fetch_enabled ?
+ intel_dp->psr.enabled &
+ BIT(INTEL_PSR2_SELECTIVE_FETCH) ?
IGNORE_PSR2_HW_TRACKING : 0);
/*
@@ -1436,7 +1456,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
*/
wm_optimization_wa(intel_dp, crtc_state);
- if (intel_dp->psr.psr2_enabled) {
+ if (intel_dp->psr.enabled & BIT(INTEL_PSR2)) {
if (DISPLAY_VER(dev_priv) == 9)
intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 0,
PSR2_VSC_ENABLE_PROG_HEADER |
@@ -1502,7 +1522,7 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp,
drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled);
- intel_dp->psr.psr2_enabled = crtc_state->has_psr2;
+ intel_dp->psr.enabled |= crtc_state->has_psr2 ? BIT(INTEL_PSR2) : 0;
intel_dp->psr.busy_frontbuffer_bits = 0;
intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
intel_dp->psr.transcoder = crtc_state->cpu_transcoder;
@@ -1510,7 +1530,8 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp,
val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6);
intel_dp->psr.dc3co_exit_delay = val;
intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline;
- intel_dp->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch;
+ intel_dp->psr.enabled |= crtc_state->enable_psr2_sel_fetch ?
+ BIT(INTEL_PSR2_SELECTIVE_FETCH) : 0;
intel_dp->psr.psr2_sel_fetch_cff_enabled = false;
intel_dp->psr.req_psr2_sdp_prior_scanline =
crtc_state->req_psr2_sdp_prior_scanline;
@@ -1519,12 +1540,12 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp,
return;
drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n",
- intel_dp->psr.psr2_enabled ? "2" : "1");
+ intel_dp->psr.enabled & BIT(INTEL_PSR2) ? "2" : "1");
intel_write_dp_vsc_sdp(encoder, crtc_state, &crtc_state->psr_vsc);
intel_snps_phy_update_psr_power_state(dev_priv, phy, true);
intel_psr_enable_sink(intel_dp);
intel_psr_enable_source(intel_dp, crtc_state);
- intel_dp->psr.enabled = true;
+ intel_dp->psr.enabled |= BIT(INTEL_PSR);
intel_dp->psr.paused = false;
intel_psr_activate(intel_dp);
@@ -1548,7 +1569,7 @@ static void intel_psr_exit(struct intel_dp *intel_dp)
return;
}
- if (intel_dp->psr.psr2_enabled) {
+ if (intel_dp->psr.enabled & BIT(INTEL_PSR2)) {
tgl_disallow_dc3co_on_psr2_exit(intel_dp);
val = intel_de_rmw(dev_priv, EDP_PSR2_CTL(cpu_transcoder),
@@ -1571,7 +1592,7 @@ static void intel_psr_wait_exit_locked(struct intel_dp *intel_dp)
i915_reg_t psr_status;
u32 psr_status_mask;
- if (intel_dp->psr.psr2_enabled) {
+ if (intel_dp->psr.enabled & BIT(INTEL_PSR2)) {
psr_status = EDP_PSR2_STATUS(cpu_transcoder);
psr_status_mask = EDP_PSR2_STATUS_STATE_MASK;
} else {
@@ -1598,7 +1619,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
return;
drm_dbg_kms(&dev_priv->drm, "Disabling PSR%s\n",
- intel_dp->psr.psr2_enabled ? "2" : "1");
+ intel_dp->psr.enabled & BIT(INTEL_PSR2) ? "2" : "1");
intel_psr_exit(intel_dp);
intel_psr_wait_exit_locked(intel_dp);
@@ -1611,7 +1632,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1,
wa_16013835468_bit_get(intel_dp), 0);
- if (intel_dp->psr.psr2_enabled) {
+ if (intel_dp->psr.enabled & BIT(INTEL_PSR2)) {
/* Wa_16012604467:adlp,mtl[a0,b0] */
if (IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0))
intel_de_rmw(dev_priv,
@@ -1627,12 +1648,10 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
/* Disable PSR on Sink */
drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0);
- if (intel_dp->psr.psr2_enabled)
+ if (intel_dp->psr.enabled & BIT(INTEL_PSR2))
drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, 0);
- intel_dp->psr.enabled = false;
- intel_dp->psr.psr2_enabled = false;
- intel_dp->psr.psr2_sel_fetch_enabled = false;
+ intel_dp->psr.enabled = 0;
intel_dp->psr.psr2_sel_fetch_cff_enabled = false;
}
@@ -1754,7 +1773,7 @@ static void psr_force_hw_tracking_exit(struct intel_dp *intel_dp)
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
- if (intel_dp->psr.psr2_sel_fetch_enabled)
+ if (intel_dp->psr.enabled & BIT(INTEL_PSR2_SELECTIVE_FETCH))
intel_de_write(dev_priv,
PSR2_MAN_TRK_CTL(cpu_transcoder),
man_trk_ctl_enable_bit_get(dev_priv) |
@@ -2180,7 +2199,7 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state,
needs_to_disable |= intel_crtc_needs_modeset(new_crtc_state);
needs_to_disable |= !new_crtc_state->has_psr;
needs_to_disable |= !new_crtc_state->active_planes;
- needs_to_disable |= new_crtc_state->has_psr2 != psr->psr2_enabled;
+ needs_to_disable |= new_crtc_state->has_psr2 != !!(psr->enabled & BIT(INTEL_PSR2));
needs_to_disable |= DISPLAY_VER(i915) < 11 &&
new_crtc_state->wm_level_disabled;
@@ -2310,7 +2329,7 @@ void intel_psr_wait_for_idle_locked(const struct intel_crtc_state *new_crtc_stat
if (!intel_dp->psr.enabled)
continue;
- if (intel_dp->psr.psr2_enabled)
+ if (intel_dp->psr.enabled & BIT(INTEL_PSR2))
ret = _psr2_ready_for_pipe_update_locked(intel_dp);
else
ret = _psr1_ready_for_pipe_update_locked(intel_dp);
@@ -2331,7 +2350,7 @@ static bool __psr_wait_for_idle_locked(struct intel_dp *intel_dp)
if (!intel_dp->psr.enabled)
return false;
- if (intel_dp->psr.psr2_enabled) {
+ if (intel_dp->psr.enabled & BIT(INTEL_PSR2)) {
reg = EDP_PSR2_STATUS(cpu_transcoder);
mask = EDP_PSR2_STATUS_STATE_MASK;
} else {
@@ -2499,7 +2518,7 @@ static void _psr_invalidate_handle(struct intel_dp *intel_dp)
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
- if (intel_dp->psr.psr2_sel_fetch_enabled) {
+ if (intel_dp->psr.enabled & BIT(INTEL_PSR2_SELECTIVE_FETCH)) {
u32 val;
if (intel_dp->psr.psr2_sel_fetch_cff_enabled) {
@@ -2572,7 +2591,8 @@ tgl_dc3co_flush_locked(struct intel_dp *intel_dp, unsigned int frontbuffer_bits,
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
- if (!intel_dp->psr.dc3co_exitline || !intel_dp->psr.psr2_enabled ||
+ if (!intel_dp->psr.dc3co_exitline ||
+ !(intel_dp->psr.enabled & BIT(INTEL_PSR2)) ||
!intel_dp->psr.active)
return;
@@ -2594,7 +2614,7 @@ static void _psr_flush_handle(struct intel_dp *intel_dp)
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
- if (intel_dp->psr.psr2_sel_fetch_enabled) {
+ if (intel_dp->psr.enabled & BIT(INTEL_PSR2_SELECTIVE_FETCH)) {
if (intel_dp->psr.psr2_sel_fetch_cff_enabled) {
/* can we turn CFF off? */
if (intel_dp->psr.busy_frontbuffer_bits == 0) {
@@ -2671,7 +2691,7 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
if (origin == ORIGIN_FLIP ||
(origin == ORIGIN_CURSOR_UPDATE &&
- !intel_dp->psr.psr2_sel_fetch_enabled)) {
+ !(intel_dp->psr.enabled & BIT(INTEL_PSR2_SELECTIVE_FETCH)))) {
tgl_dc3co_flush_locked(intel_dp, frontbuffer_bits, origin);
goto unlock;
}
@@ -2718,7 +2738,7 @@ void intel_psr_init(struct intel_dp *intel_dp)
return;
}
- intel_dp->psr.source_support = true;
+ intel_dp->psr.source_support |= BIT(INTEL_PSR);
/* Set link_standby x link_off defaults */
if (DISPLAY_VER(dev_priv) < 12)
@@ -2757,7 +2777,7 @@ static void psr_alpm_check(struct intel_dp *intel_dp)
u8 val;
int r;
- if (!psr->psr2_enabled)
+ if (!(psr->enabled & BIT(INTEL_PSR2)))
return;
r = drm_dp_dpcd_readb(aux, DP_RECEIVER_ALPM_STATUS, &val);
@@ -2926,7 +2946,7 @@ psr_source_status(struct intel_dp *intel_dp, struct seq_file *m)
const char *status = "unknown";
u32 val, status_val;
- if (intel_dp->psr.psr2_enabled) {
+ if (intel_dp->psr.enabled & BIT(INTEL_PSR2)) {
static const char * const live_status[] = {
"IDLE",
"CAPTURE",
@@ -2974,19 +2994,19 @@ static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp)
bool enabled;
u32 val;
- seq_printf(m, "Sink support: %s", str_yes_no(psr->sink_support));
- if (psr->sink_support)
+ seq_printf(m, "Sink support: %s", str_yes_no(psr->sink_support & BIT(INTEL_PSR)));
+ if (psr->sink_support & BIT(INTEL_PSR))
seq_printf(m, " [0x%02x]", intel_dp->psr_dpcd[0]);
seq_puts(m, "\n");
- if (!psr->sink_support)
+ if (!(psr->sink_support & BIT(INTEL_PSR)))
return 0;
wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
mutex_lock(&psr->lock);
if (psr->enabled)
- status = psr->psr2_enabled ? "PSR2 enabled" : "PSR1 enabled";
+ status = psr->enabled & BIT(INTEL_PSR2) ? "PSR2 enabled" : "PSR1 enabled";
else
status = "disabled";
seq_printf(m, "PSR mode: %s\n", status);
@@ -2998,7 +3018,7 @@ static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp)
goto unlock;
}
- if (psr->psr2_enabled) {
+ if (psr->enabled & BIT(INTEL_PSR2)) {
val = intel_de_read(dev_priv, EDP_PSR2_CTL(cpu_transcoder));
enabled = val & EDP_PSR2_ENABLE;
} else {
@@ -3024,7 +3044,7 @@ static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp)
seq_printf(m, "Last exit at: %lld\n", psr->last_exit);
}
- if (psr->psr2_enabled) {
+ if (psr->enabled & BIT(INTEL_PSR2)) {
u32 su_frames_val[3];
int frame;
@@ -3049,7 +3069,7 @@ static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp)
}
seq_printf(m, "PSR2 selective fetch: %s\n",
- str_enabled_disabled(psr->psr2_sel_fetch_enabled));
+ str_enabled_disabled(psr->enabled & BIT(INTEL_PSR2_SELECTIVE_FETCH)));
}
unlock:
--
2.34.1
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