[PATCH 2/2] drm/i915/psr: Convert crtc_state->has_psr* to crtc_state->psr_mode
Jouni Högander
jouni.hogander at intel.com
Tue Sep 5 09:32:28 UTC 2023
PSR code is already internally using flags instead of booleans. Convert
crtc_state->has_psr to crtc_state->psr_mode as well.
Signed-off-by: Jouni Högander <jouni.hogander at intel.com>
---
drivers/gpu/drm/i915/display/intel_color.c | 4 +-
drivers/gpu/drm/i915/display/intel_display.c | 8 ++--
.../drm/i915/display/intel_display_types.h | 4 +-
drivers/gpu/drm/i915/display/intel_dp.c | 12 ++---
drivers/gpu/drm/i915/display/intel_fbc.c | 4 +-
drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +-
drivers/gpu/drm/i915/display/intel_pipe_crc.c | 2 +-
drivers/gpu/drm/i915/display/intel_psr.c | 48 +++++++++----------
8 files changed, 38 insertions(+), 46 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 5918e2e9bcdd..eab7f02d186f 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -979,7 +979,7 @@ static void skl_color_commit_noarm(const struct intel_crtc_state *crtc_state)
* register programming will be peformed from skl_color_commit_arm()
* which is called after PSR exit.
*/
- if (!crtc_state->has_psr)
+ if (!crtc_state->psr_mode)
ilk_load_csc_matrix(crtc_state);
}
@@ -1084,7 +1084,7 @@ static void skl_color_commit_arm(const struct intel_crtc_state *crtc_state)
enum pipe pipe = crtc->pipe;
u32 val = 0;
- if (crtc_state->has_psr)
+ if (crtc_state->psr_mode)
ilk_load_csc_matrix(crtc_state);
/*
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index f6397462e4c2..1645173d4fb6 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5102,7 +5102,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
} while (0)
#define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \
- if (!current_config->has_psr && !pipe_config->has_psr && \
+ if (!current_config->psr_mode && !pipe_config->psr_mode && \
!intel_compare_dp_vsc_sdp(¤t_config->infoframes.name, \
&pipe_config->infoframes.name)) { \
pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset, __stringify(name), \
@@ -5255,9 +5255,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
PIPE_CONF_CHECK_CSC(output_csc);
if (current_config->active_planes) {
- PIPE_CONF_CHECK_BOOL(has_psr);
- PIPE_CONF_CHECK_BOOL(has_psr2);
- PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch);
+ PIPE_CONF_CHECK_I(psr_mode);
PIPE_CONF_CHECK_I(dc3co_exitline);
}
}
@@ -5315,7 +5313,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
PIPE_CONF_CHECK_I(min_voltage_level);
- if (current_config->has_psr || pipe_config->has_psr)
+ if (current_config->psr_mode || pipe_config->psr_mode)
PIPE_CONF_CHECK_X_WITH_MASK(infoframes.enable,
~intel_hdmi_infoframe_enable(DP_SDP_VSC));
else
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 672ac676fbcb..7b8c4357cc10 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1198,9 +1198,7 @@ struct intel_crtc_state {
bool seamless_m_n;
/* PSR is supported but might not be enabled due the lack of enabled planes */
- bool has_psr;
- bool has_psr2;
- bool enable_psr2_sel_fetch;
+ u32 psr_mode;
bool req_psr2_sdp_prior_scanline;
bool wm_level_disabled;
u32 dc3co_exitline;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 3faa68989d85..5d3443a916e3 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2418,7 +2418,7 @@ static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
struct drm_dp_vsc_sdp *vsc = &crtc_state->infoframes.vsc;
/* When a crtc state has PSR, VSC SDP will be handled by PSR routine */
- if (crtc_state->has_psr)
+ if (crtc_state->psr_mode)
return;
if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state))
@@ -2437,7 +2437,7 @@ void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
{
vsc->sdp_type = DP_SDP_VSC;
- if (crtc_state->has_psr2) {
+ if (crtc_state->psr_mode & BIT(INTEL_PSR2)) {
if (intel_dp->psr.colorimetry_support &&
intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
/* [PSR2, +Colorimetry] */
@@ -2511,7 +2511,7 @@ static bool can_enable_drrs(struct intel_connector *connector,
* so to guarantee this, intel_drrs_compute_config() must be called
* after intel_psr_compute_config().
*/
- if (pipe_config->has_psr)
+ if (pipe_config->psr_mode)
return false;
/* FIXME missing FDI M2/N2 etc. */
@@ -3932,7 +3932,7 @@ void intel_dp_set_infoframes(struct intel_encoder *encoder,
/* TODO: Add DSC case (DIP_ENABLE_PPS) */
/* When PSR is enabled, this routine doesn't disable VSC DIP */
- if (!crtc_state->has_psr)
+ if (!crtc_state->psr_mode)
val &= ~VIDEO_DIP_ENABLE_VSC_HSW;
intel_de_write(dev_priv, reg, val);
@@ -3942,7 +3942,7 @@ void intel_dp_set_infoframes(struct intel_encoder *encoder,
return;
/* When PSR is enabled, VSC SDP is handled by PSR routine */
- if (!crtc_state->has_psr)
+ if (!crtc_state->psr_mode)
intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);
intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);
@@ -4075,7 +4075,7 @@ static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder,
int ret;
/* When PSR is enabled, VSC SDP is handled by PSR routine */
- if (crtc_state->has_psr)
+ if (crtc_state->psr_mode)
return;
if ((crtc_state->infoframes.enable &
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 817e5784660b..12a0174e7c82 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -1094,7 +1094,7 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state,
* Recommendation is to keep this combination disabled
* Bspec: 50422 HSD: 14010260002
*/
- if (DISPLAY_VER(i915) >= 12 && crtc_state->has_psr2) {
+ if (DISPLAY_VER(i915) >= 12 && crtc_state->psr_mode & BIT(INTEL_PSR2)) {
plane_state->no_fbc_reason = "PSR2 enabled";
return 0;
}
@@ -1102,7 +1102,7 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state,
/* Wa_14016291713 */
if ((IS_DISPLAY_VER(i915, 12, 13) ||
IS_DISPLAY_IP_STEP(i915, IP_VER(14, 0), STEP_A0, STEP_C0)) &&
- crtc_state->has_psr) {
+ crtc_state->psr_mode) {
plane_state->no_fbc_reason = "PSR1 enabled (Wa_14016291713)";
return 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index bc564326037a..2c4c3d74e7f5 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -523,7 +523,7 @@ void hsw_write_infoframe(struct intel_encoder *encoder,
0);
/* Wa_14013475917 */
- if (IS_DISPLAY_VER(dev_priv, 13, 14) && crtc_state->has_psr && type == DP_SDP_VSC)
+ if (IS_DISPLAY_VER(dev_priv, 13, 14) && crtc_state->psr_mode && type == DP_SDP_VSC)
return;
val |= hsw_infoframe_enable(type);
diff --git a/drivers/gpu/drm/i915/display/intel_pipe_crc.c b/drivers/gpu/drm/i915/display/intel_pipe_crc.c
index 5a468ed6e26c..36c2ba3766fe 100644
--- a/drivers/gpu/drm/i915/display/intel_pipe_crc.c
+++ b/drivers/gpu/drm/i915/display/intel_pipe_crc.c
@@ -302,7 +302,7 @@ intel_crtc_crc_setup_workarounds(struct intel_crtc *crtc, bool enable)
goto put_state;
}
- pipe_config->uapi.mode_changed = pipe_config->has_psr;
+ pipe_config->uapi.mode_changed = pipe_config->psr_mode;
pipe_config->crc_enabled = enable;
if (IS_HASWELL(dev_priv) &&
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 39c8baf87661..863e28692c39 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -928,7 +928,7 @@ tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp,
* DMC's DC3CO exit mechanism has an issue with Selective Fecth
* TODO: when the issue is addressed, this restriction should be removed.
*/
- if (crtc_state->enable_psr2_sel_fetch)
+ if (crtc_state->psr_mode & BIT(INTEL_PSR2_SELECTIVE_FETCH))
return;
if (!(power_domains->allowed_dc_mask & DC_STATE_EN_DC3CO))
@@ -972,7 +972,7 @@ static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
return false;
}
- return crtc_state->enable_psr2_sel_fetch = true;
+ return crtc_state->psr_mode |= BIT(INTEL_PSR2_SELECTIVE_FETCH);
}
static bool psr2_granularity_check(struct intel_dp *intel_dp,
@@ -992,7 +992,7 @@ static bool psr2_granularity_check(struct intel_dp *intel_dp,
return false;
/* HW tracking is only aligned to 4 lines */
- if (!crtc_state->enable_psr2_sel_fetch)
+ if (!(crtc_state->psr_mode & BIT(INTEL_PSR2_SELECTIVE_FETCH)))
return intel_dp->psr.su_y_granularity == 4;
/*
@@ -1205,7 +1205,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
goto unsupported;
}
- if (!crtc_state->enable_psr2_sel_fetch &&
+ if (!(crtc_state->psr_mode & BIT(INTEL_PSR2_SELECTIVE_FETCH)) &&
(crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v)) {
drm_dbg_kms(&dev_priv->drm,
"PSR2 not enabled, resolution %dx%d > max supported %dx%d\n",
@@ -1218,7 +1218,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
return true;
unsupported:
- crtc_state->enable_psr2_sel_fetch = false;
+ crtc_state->psr_mode &= ~BIT(INTEL_PSR2_SELECTIVE_FETCH);
return false;
}
@@ -1274,8 +1274,9 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
return;
}
- crtc_state->has_psr = true;
- crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state);
+ crtc_state->psr_mode |= BIT(INTEL_PSR);
+ crtc_state->psr_mode |= intel_psr2_config_valid(intel_dp, crtc_state) ?
+ BIT(INTEL_PSR2) : 0;
crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state, conn_state,
@@ -1306,8 +1307,7 @@ void intel_psr_get_config(struct intel_encoder *encoder,
* Not possible to read EDP_PSR/PSR2_CTL registers as it is
* enabled/disabled because of frontbuffer tracking and others.
*/
- pipe_config->has_psr = true;
- pipe_config->has_psr2 = intel_dp->psr.enabled & BIT(INTEL_PSR2);
+ pipe_config->psr_mode = intel_dp->psr.enabled & ~BIT(INTEL_PSR2_SELECTIVE_FETCH);
pipe_config->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
if (!(intel_dp->psr.enabled & BIT(INTEL_PSR2)))
@@ -1316,7 +1316,7 @@ void intel_psr_get_config(struct intel_encoder *encoder,
if (HAS_PSR2_SEL_FETCH(dev_priv)) {
val = intel_de_read(dev_priv, PSR2_MAN_TRK_CTL(cpu_transcoder));
if (val & PSR2_MAN_TRK_CTL_ENABLE)
- pipe_config->enable_psr2_sel_fetch = true;
+ pipe_config->psr_mode |= BIT(INTEL_PSR2_SELECTIVE_FETCH);
}
if (DISPLAY_VER(dev_priv) >= 12) {
@@ -1522,7 +1522,6 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp,
drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled);
- intel_dp->psr.enabled |= crtc_state->has_psr2 ? BIT(INTEL_PSR2) : 0;
intel_dp->psr.busy_frontbuffer_bits = 0;
intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
intel_dp->psr.transcoder = crtc_state->cpu_transcoder;
@@ -1530,8 +1529,6 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp,
val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6);
intel_dp->psr.dc3co_exit_delay = val;
intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline;
- intel_dp->psr.enabled |= crtc_state->enable_psr2_sel_fetch ?
- BIT(INTEL_PSR2_SELECTIVE_FETCH) : 0;
intel_dp->psr.psr2_sel_fetch_cff_enabled = false;
intel_dp->psr.req_psr2_sdp_prior_scanline =
crtc_state->req_psr2_sdp_prior_scanline;
@@ -1539,13 +1536,13 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp,
if (!psr_interrupt_error_check(intel_dp))
return;
+ intel_dp->psr.enabled = crtc_state->psr_mode;
drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n",
intel_dp->psr.enabled & BIT(INTEL_PSR2) ? "2" : "1");
intel_write_dp_vsc_sdp(encoder, crtc_state, &crtc_state->psr_vsc);
intel_snps_phy_update_psr_power_state(dev_priv, phy, true);
intel_psr_enable_sink(intel_dp);
intel_psr_enable_source(intel_dp, crtc_state);
- intel_dp->psr.enabled |= BIT(INTEL_PSR);
intel_dp->psr.paused = false;
intel_psr_activate(intel_dp);
@@ -1667,7 +1664,7 @@ void intel_psr_disable(struct intel_dp *intel_dp,
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- if (!old_crtc_state->has_psr)
+ if (!old_crtc_state->psr_mode)
return;
if (drm_WARN_ON(&dev_priv->drm, !CAN_PSR(intel_dp)))
@@ -1803,7 +1800,7 @@ void intel_psr2_disable_plane_sel_fetch_arm(struct intel_plane *plane,
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum pipe pipe = plane->pipe;
- if (!crtc_state->enable_psr2_sel_fetch)
+ if (!(crtc_state->psr_mode & BIT(INTEL_PSR2_SELECTIVE_FETCH)))
return;
intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), 0);
@@ -1816,7 +1813,7 @@ void intel_psr2_program_plane_sel_fetch_arm(struct intel_plane *plane,
struct drm_i915_private *i915 = to_i915(plane->base.dev);
enum pipe pipe = plane->pipe;
- if (!crtc_state->enable_psr2_sel_fetch)
+ if (!(crtc_state->psr_mode & BIT(INTEL_PSR2_SELECTIVE_FETCH)))
return;
if (plane->id == PLANE_CURSOR)
@@ -1838,7 +1835,7 @@ void intel_psr2_program_plane_sel_fetch_noarm(struct intel_plane *plane,
u32 val;
int x, y;
- if (!crtc_state->enable_psr2_sel_fetch)
+ if (!(crtc_state->psr_mode & BIT(INTEL_PSR2_SELECTIVE_FETCH)))
return;
if (plane->id == PLANE_CURSOR)
@@ -1878,7 +1875,7 @@ void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_st
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
struct intel_encoder *encoder;
- if (!crtc_state->enable_psr2_sel_fetch)
+ if (!(crtc_state->psr_mode & BIT(INTEL_PSR2_SELECTIVE_FETCH)))
return;
for_each_intel_encoder_mask_with_psr(&dev_priv->drm, encoder,
@@ -2012,7 +2009,7 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
bool full_update = false;
int i, ret;
- if (!crtc_state->enable_psr2_sel_fetch)
+ if (!(crtc_state->psr_mode & BIT(INTEL_PSR2_SELECTIVE_FETCH)))
return 0;
if (!psr2_sel_fetch_pipe_state_supported(crtc_state)) {
@@ -2197,9 +2194,8 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state,
* - Display WA #1136: skl, bxt
*/
needs_to_disable |= intel_crtc_needs_modeset(new_crtc_state);
- needs_to_disable |= !new_crtc_state->has_psr;
needs_to_disable |= !new_crtc_state->active_planes;
- needs_to_disable |= new_crtc_state->has_psr2 != !!(psr->enabled & BIT(INTEL_PSR2));
+ needs_to_disable |= new_crtc_state->psr_mode != psr->enabled;
needs_to_disable |= DISPLAY_VER(i915) < 11 &&
new_crtc_state->wm_level_disabled;
@@ -2219,7 +2215,7 @@ static void _intel_psr_post_plane_update(const struct intel_atomic_state *state,
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct intel_encoder *encoder;
- if (!crtc_state->has_psr)
+ if (!crtc_state->psr_mode)
return;
for_each_intel_encoder_mask_with_psr(state->base.dev, encoder,
@@ -2316,7 +2312,7 @@ void intel_psr_wait_for_idle_locked(const struct intel_crtc_state *new_crtc_stat
struct drm_i915_private *dev_priv = to_i915(new_crtc_state->uapi.crtc->dev);
struct intel_encoder *encoder;
- if (!new_crtc_state->has_psr)
+ if (!new_crtc_state->psr_mode)
return;
for_each_intel_encoder_mask_with_psr(&dev_priv->drm, encoder,
@@ -2903,7 +2899,7 @@ void intel_psr_lock(const struct intel_crtc_state *crtc_state)
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
struct intel_encoder *encoder;
- if (!crtc_state->has_psr)
+ if (!crtc_state->psr_mode)
return;
for_each_intel_encoder_mask_with_psr(&i915->drm, encoder,
@@ -2926,7 +2922,7 @@ void intel_psr_unlock(const struct intel_crtc_state *crtc_state)
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
struct intel_encoder *encoder;
- if (!crtc_state->has_psr)
+ if (!crtc_state->psr_mode)
return;
for_each_intel_encoder_mask_with_psr(&i915->drm, encoder,
--
2.34.1
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