[PATCH 3/4] drm/i915/vrr: Avoid reading/writing VTOTAL when vrr is enabled

[Ankit Nautiyal]

With VRR, we are using VRR timing generator and VRR VMAX/MIN registers
instead of VTOTAL. So avoid reading/writing VTOTAL regsiter when VRR is
enabled. To fill adjusted_mode->crtc_vdisplay/vtotal use VRR MAX
register, in intel_vrr_get_config.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal at intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 33 +++++++++++---------
 drivers/gpu/drm/i915/display/intel_vrr.c     |  3 ++
 2 files changed, 22 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 2e46efba3376..a20a6bf41524 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2713,10 +2713,9 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
 	intel_de_write(dev_priv, TRANS_HSYNC(cpu_transcoder),
 		       HSYNC_START(adjusted_mode->crtc_hsync_start - 1) |
 		       HSYNC_END(adjusted_mode->crtc_hsync_end - 1));
-
-	intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder),
-		       VACTIVE(crtc_vdisplay - 1) |
-		       VTOTAL(crtc_vtotal - 1));
+	if (!crtc_state->vrr.enable)
+		intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder),
+			       VACTIVE(crtc_vdisplay - 1) | VTOTAL(crtc_vtotal - 1));
 	intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),
 		       VBLANK_START(crtc_vblank_start - 1) |
 		       VBLANK_END(crtc_vblank_end - 1));
@@ -2757,13 +2756,16 @@ static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc
 	intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),
 		       VBLANK_START(crtc_vblank_start - 1) |
 		       VBLANK_END(crtc_vblank_end - 1));
-	/*
-	 * The double buffer latch point for TRANS_VTOTAL
-	 * is the transcoder's undelayed vblank.
-	 */
-	intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder),
-		       VACTIVE(crtc_vdisplay - 1) |
-		       VTOTAL(crtc_vtotal - 1));
+
+	/* FIXME: Check if we need to write VMAX register here */
+	if (!crtc_state->vrr.enable)
+		/*
+		 * The double buffer latch point for TRANS_VTOTAL
+		 * is the transcoder's undelayed vblank.
+		 */
+		intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder),
+			       VACTIVE(crtc_vdisplay - 1) |
+			       VTOTAL(crtc_vtotal - 1));
 }
 
 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
@@ -2819,9 +2821,12 @@ static void intel_get_transcoder_timings(struct intel_crtc *crtc,
 	adjusted_mode->crtc_hsync_start = REG_FIELD_GET(HSYNC_START_MASK, tmp) + 1;
 	adjusted_mode->crtc_hsync_end = REG_FIELD_GET(HSYNC_END_MASK, tmp) + 1;
 
-	tmp = intel_de_read(dev_priv, TRANS_VTOTAL(cpu_transcoder));
-	adjusted_mode->crtc_vdisplay = REG_FIELD_GET(VACTIVE_MASK, tmp) + 1;
-	adjusted_mode->crtc_vtotal = REG_FIELD_GET(VTOTAL_MASK, tmp) + 1;
+	/* When VRR is enabled, crtc_vdisplay/vtotal are filled in vrr_get_config */
+	if (!pipe_config->vrr.enable) {
+		tmp = intel_de_read(dev_priv, TRANS_VTOTAL(cpu_transcoder));
+		adjusted_mode->crtc_vdisplay = REG_FIELD_GET(VACTIVE_MASK, tmp) + 1;
+		adjusted_mode->crtc_vtotal = REG_FIELD_GET(VTOTAL_MASK, tmp) + 1;
+	}
 
 	/* FIXME TGL+ DSI transcoders have this! */
 	if (!transcoder_is_dsi(cpu_transcoder)) {
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 894ee97b3e1b..cdb2c224647c 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -289,6 +289,7 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
 void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
+	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 	u32 trans_vrr_ctl, trans_vrr_vsync;
 
@@ -321,5 +322,7 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
 			crtc_state->vrr.vsync_end =
 				REG_FIELD_GET(VRR_VSYNC_END_MASK, trans_vrr_vsync);
 		}
+		adjusted_mode->crtc_vtotal = crtc_state->vrr.vmax;
+		adjusted_mode->crtc_vdisplay = intel_vrr_vmin_vblank_start(crtc_state);
 	}
 }
-- 
2.40.1