[PATCH] drm/i915/ddi: Sanitize DDI BUF during HW readout

[Imre Deak]

Signed-off-by: Imre Deak <imre.deak at intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c      | 41 ++++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_ddi.h      |  2 +-
 .../drm/i915/display/intel_modeset_setup.c    |  2 +-
 3 files changed, 41 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index acb986bc1f33a..2496e14e64936 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -192,6 +192,11 @@ static void mtl_wait_ddi_buf_idle(struct drm_i915_private *i915, enum port port)
 void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
 			     enum port port)
 {
+	if (DISPLAY_VER(dev_priv) >= 14) {
+		mtl_wait_ddi_buf_idle(dev_priv, port);
+		return;
+	}
+
 	if (IS_BROXTON(dev_priv)) {
 		udelay(16);
 		return;
@@ -2057,7 +2062,37 @@ void intel_ddi_disable_clock(struct intel_encoder *encoder)
 		encoder->disable_clock(encoder);
 }
 
-void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
+
+static void sanitize_ddi_buf(struct intel_encoder *encoder)
+{
+	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+	enum port port = encoder->port;
+	intel_wakeref_t wakeref;
+	u32 val;
+
+	if (encoder->base.crtc)
+		return;
+
+	wakeref = intel_display_power_get_if_enabled(i915, encoder->power_domain);
+	if (!wakeref)
+		return;
+
+	val = intel_de_read(i915, DDI_BUF_CTL(port));
+	if (val & DDI_BUF_CTL_ENABLE) {
+		drm_dbg_kms(&i915->drm,
+			    "[ENCODER:%d:%s] DDI_BUF enabled on an inactive port, disable it\n",
+			    encoder->base.base.id, encoder->base.name);
+
+		val &= ~DDI_BUF_CTL_ENABLE;
+		intel_de_write(i915, DDI_BUF_CTL(port), val);
+
+		intel_wait_ddi_buf_idle(i915, port);
+	}
+
+	intel_display_power_put(i915, encoder->power_domain, wakeref);
+}
+
+void intel_ddi_sanitize_encoder(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 	u32 port_mask;
@@ -2070,6 +2105,8 @@ void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
 	if (encoder->type == INTEL_OUTPUT_DP_MST)
 		return;
 
+	sanitize_ddi_buf(encoder);
+
 	if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) {
 		u8 pipe_mask;
 		bool is_mst;
@@ -3056,7 +3093,7 @@ static void mtl_disable_ddi_buf(struct intel_encoder *encoder,
 		intel_de_write(dev_priv, DDI_BUF_CTL(port), val);
 
 		/* 3.c Poll for PORT_BUF_CTL Idle Status == 1, timeout after 100us */
-		mtl_wait_ddi_buf_idle(dev_priv, port);
+		intel_wait_ddi_buf_idle(dev_priv, port);
 	}
 
 	/* 3.d Disable D2D Link */
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h b/drivers/gpu/drm/i915/display/intel_ddi.h
index 2faadd1441e2f..6e72720daa620 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.h
+++ b/drivers/gpu/drm/i915/display/intel_ddi.h
@@ -79,7 +79,7 @@ void intel_ddi_compute_min_voltage_level(struct intel_crtc_state *crtc_state);
 int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder,
 			       enum transcoder cpu_transcoder,
 			       bool enable, u32 hdcp_mask);
-void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder);
+void intel_ddi_sanitize_encoder(struct intel_encoder *encoder);
 int intel_ddi_level(struct intel_encoder *encoder,
 		    const struct intel_crtc_state *crtc_state,
 		    int lane);
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
index 9a2bea19f17b7..9cb73deb1d37d 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
@@ -662,7 +662,7 @@ static void intel_sanitize_encoder(struct intel_encoder *encoder)
 	intel_opregion_notify_encoder(encoder, connector && has_active_crtc);
 
 	if (HAS_DDI(i915))
-		intel_ddi_sanitize_encoder_pll_mapping(encoder);
+		intel_ddi_sanitize_encoder(encoder);
 }
 
 /* FIXME read out full plane state for all planes */
-- 
2.44.2