[PATCH 00/27] Use VRR timing generator for fixed refresh rate modes

Ankit Nautiyal ankit.k.nautiyal at intel.com
Thu Jan 16 08:51:34 UTC 2025


Even though the VRR timing generator (TG) is primarily used for
variable refresh rates, it can be used for fixed refresh rates as
well. For a fixed refresh rate the Flip Line and Vmax must be equal
(TRANS_VRR_FLIPLINE = TRANS_VRR_VMAX). Beyond that, there are some
dependencies between the VRR timings and the legacy timing generator
registers.

This series is an attempt to use VRR TG for fixed refresh rate.
For platforms MTL+, always go with VRR timing generator for both fixed and
variable refresh rate cases.

Ankit Nautiyal (27):
  drm/i915/vrr: Remove unwanted comment
  drm/i915:vrr: Refactor VRR timing setup into a separate function
  drm/i915:vrr: Separate out functions to compute vmin and vmax
  drm/i915/vrr: Make helpers for cmrr and vrr timings
  drm/i915/vrr: Avoid prepare vrr timings for cmrr
  drm/i915/vrr: Simplify CMRR Enable Check in intel_vrr_get_config
  drm/i915/vrr: Introduce new field for VRR mode
  drm/i915/vrr: Fill VRR timing generator mode for CMRR and VRR
  drm/i915/display: Remove vrr.enable and instead check vrr.mode != NONE
  drm/i915/display: Absorb cmrr attributes into vrr struct
  drm/i915/display: Add vrr mode to crtc_state dump
  drm/i915/dp: Avoid vrr compute config for HDMI sink
  drm/i915/vrr: Introduce VRR mode Fixed RR
  drm/i915/vrr: Fill fixed refresh mode in vrr_get_compute_config
  drm/i915/vrr: Avoid sending PUSH when VRR TG is used with Fixed
    refresh rate
  drm/i915/display: Enable MSA Ignore Timing PAR only when in not
    fixed_rr mode
  drm/i915/vrr: Disable CMRR
  drm/i915/vrr: Use crtc_vtotal for vmin
  drm/i915/vrr: Always set vrr vmax/vmin/flipline in
    vrr_{enable/disable}
  drm/i915/dp: fix the Adaptive sync Operation mode for SDP
  drm/i915/hdmi: Use VRR Timing generator for HDMI
  drm/i915/vrr: Handle joiner with vrr
  drm/i915/display: Disable PSR before disabling VRR
  drm/i915/psr: Allow PSR for fixed refrsh rate with VRR TG
  drm/i915/display: Extend WA 14015406119 for PSR2
  drm/i915/vrr: Always use VRR timing generator for MTL+
  drm/i915/display: Use VRR timings for MTL+ in modeset sequence

 .../drm/i915/display/intel_crtc_state_dump.c  |  20 +-
 drivers/gpu/drm/i915/display/intel_ddi.c      |   3 +-
 drivers/gpu/drm/i915/display/intel_display.c  |  56 ++---
 .../drm/i915/display/intel_display_types.h    |  17 +-
 drivers/gpu/drm/i915/display/intel_dp.c       |  17 +-
 .../drm/i915/display/intel_dp_link_training.c |   8 +-
 drivers/gpu/drm/i915/display/intel_dsb.c      |   2 +-
 drivers/gpu/drm/i915/display/intel_hdmi.c     |   3 +
 .../drm/i915/display/intel_modeset_setup.c    |   3 +-
 drivers/gpu/drm/i915/display/intel_psr.c      |   7 +-
 drivers/gpu/drm/i915/display/intel_vblank.c   |   8 +-
 drivers/gpu/drm/i915/display/intel_vrr.c      | 231 ++++++++++++------
 drivers/gpu/drm/i915/display/intel_vrr.h      |   1 +
 drivers/gpu/drm/i915/display/skl_watermark.c  |   3 +-
 14 files changed, 249 insertions(+), 130 deletions(-)

-- 
2.45.2



More information about the Intel-gfx-trybot mailing list