[Intel-gfx] [PATCH] drm/i915: enable memory self refresh on 945GM

[Jesse Barnes]

On Wed, 02 Dec 2009 23:11:44 +0800
Li Peng <peng.li at linux.intel.com> wrote:
> > > Thanks for pointing out, I will fix it.
> > 
> > It seems that we should also use the FIFO_MASK/FIFO_EN on 945G
> > platform.
> > 
> 
> Yeah, should add 945G.

Thanks for catching this.  It seems all the chipset variations have
slightly different register layouts for this feature.

> > Do you mean that the system can't be booted correctly if we enable
> > the SR bit in i9xx_update_wm?
> > 
> > How about setting the another self-refresh watermark?
> 
> System boot correctly, I got screen freeze immediately after booting
> into desktop, can't click anything, but VT switch and system network
> works. 
> 
> how to calculate another self-refresh watermark ? I tried some random
> value, doesn't help.

On 915 I think you'll have to set the SR watermark to a very low
value.  But the docs are unclear; it may re-use the existing plane A
watermark if INSTPM:12 is set?  In that case you'd need to set both of
them to a low value, preferably with a high burst value.

But we should definitely get the 945 fix in ASAP and cc stable, can you
re-post with the fixes?

Thanks,
-- 
Jesse Barnes, Intel Open Source Technology Center