[Intel-gfx] [PATCH] drm/i915: enable memory self refresh on 945GM

[Jesse Barnes]

On Fri, 4 Dec 2009 12:20:25 -0800
Jesse Barnes <jbarnes at virtuousgeek.org> wrote:

> On Wed, 02 Dec 2009 23:11:44 +0800
> Li Peng <peng.li at linux.intel.com> wrote:
> > > > Thanks for pointing out, I will fix it.
> > > 
> > > It seems that we should also use the FIFO_MASK/FIFO_EN on 945G
> > > platform.
> > > 
> > 
> > Yeah, should add 945G.
> 
> Thanks for catching this.  It seems all the chipset variations have
> slightly different register layouts for this feature.
> 
> > > Do you mean that the system can't be booted correctly if we enable
> > > the SR bit in i9xx_update_wm?
> > > 
> > > How about setting the another self-refresh watermark?
> > 
> > System boot correctly, I got screen freeze immediately after booting
> > into desktop, can't click anything, but VT switch and system network
> > works. 
> > 
> > how to calculate another self-refresh watermark ? I tried some
> > random value, doesn't help.
> 
> On 915 I think you'll have to set the SR watermark to a very low
> value.  But the docs are unclear; it may re-use the existing plane A
> watermark if INSTPM:12 is set?  In that case you'd need to set both of
> them to a low value, preferably with a high burst value.
> 
> But we should definitely get the 945 fix in ASAP and cc stable, can
> you re-post with the fixes?

I'm testing this now on my 945GME and 915GM systems, seems solid on my
945GME so far (building on my slow 915 system now).  Peng, can you
confirm it works for you too?

-- 
Jesse Barnes, Intel Open Source Technology Center

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6b59602..09d9a86 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -306,11 +306,14 @@
 #define   I915_ERROR_MEMORY_REFRESH			(1<<1)
 #define   I915_ERROR_INSTRUCTION			(1<<0)
 #define INSTPM	        0x020c0
+#define   INSTPM_SELF_EN (1<<12) /* 915M only */
 #define ACTHD	        0x020c8
 #define FW_BLC		0x020d8
 #define FW_BLC2	 	0x020dc
 #define FW_BLC_SELF	0x020e0 /* 915+ only */
-#define   FW_BLC_SELF_EN (1<<15)
+#define   FW_BLC_SELF_EN_MASK (1<<31)
+#define   FW_BLC_SELF_WM_MASK (1<<16) /* 945 only */
+#define   FW_BLC_SELF_EN (1<<15) /* 945 only */
 #define MM_BURST_LENGTH     0x00700000
 #define MM_FIFO_WATERMARK   0x0001F000
 #define LM_BURST_LENGTH     0x00000700
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 65b76ff..7def2bf 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2682,7 +2682,17 @@ static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
 		srwm = total_size - sr_entries;
 		if (srwm < 0)
 			srwm = 1;
-		I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN | (srwm & 0x3f));
+		/* 945 needs register unprotected first */
+		if (IS_I945G(dev) || IS_I945GM(dev)) {
+			I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK |
+				   FW_BLC_SELF_WM_MASK | FW_BLC_SELF_EN |
+				   (srwm & 0xff));
+			POSTING_READ(FW_BLC_SELF);
+		} else if (IS_I915GM(dev)) {
+			/* 915M has a smaller SRWM field */
+			I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
+			I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
+		}
 	}
 
 	DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",