[Intel-gfx] [PATCH 1/2] drm/i915: Use same DPLL calculation logic to calculate the LVDS downclock and normal clock

[ykzhao]

On Wed, 2009-12-16 at 02:35 +0800, Matthew Garrett wrote:
> On Tue, Dec 15, 2009 at 09:13:51PM +0800, yakui.zhao at intel.com wrote:
> 
> > According to the spec only one M/N/P combination is appropriate for one given
> > clock regardless of normal clock or reduced downclock. This M/N/P combination
> > is defined in one spreadsheet(Of course our code uses the find_pll callback
> > function to calculate the M/N/P instead of looking up it in table). In theory
> > we should get the same DPLL divider factor(P) for the normal clock and reduced
> > downclock when the LVDS reduced downclock is found on one laptop.
> > If we get the diferent divider factor(P) for normal clock and reduced
> > clock, the reduced downclock is incorrect and should be discarded.
> 
> What is the potential downside of using an "incorrect" M/N/P?

We can't get the correct display clock and the screen will be flicker.
Sometimes the dpll can't work correctly.

Thanks.
    Yakui.
>