[Intel-gfx] [RFC] support tiled rendering on pre-965 chips

[Jesse Barnes]

On Friday, January 23, 2009 2:08 pm Jesse Barnes wrote:
> With DRI2 and UXA we don't actually tile back, depth or fake front buffers
> like we should on pre-965 chips, since they require fence regs to be set up
> in order to render properly.
>
> This patchset re-adds basic support for tiled rendering on pre-965 in some
> configurations.  It's been lightly tested on 915GM and 945GM so far,
> additional testing is welcome.  It seems to make a good difference on most
> 3D rendering, but doesn't quite bring it back up to DRI1 levels, so more
> optimization is still needed.  It also won't work on machines with the bit
> 17 XOR randomization applied, since the swizzling in that configuration
> isn't supported yet.

Here's what I've been using to see the regs with intel_reg_dumper.


-- 
Jesse Barnes, Intel Open Source Technology Center
-------------- next part --------------
A non-text attachment was scrubbed...
Name: i830-debug-old-fence-regs.patch
Type: text/x-diff
Size: 813 bytes
Desc: not available
URL: <http://lists.freedesktop.org/archives/intel-gfx/attachments/20090123/06a13f92/attachment.patch>