[Intel-gfx] [PATCH 1/2] drm: Fix EDID detailed timing misc flags decoding
keithp at keithp.com
Fri Jun 26 02:57:47 CEST 2009
On Thu, 2009-06-25 at 16:50 -0700, Jesse Barnes wrote:
> Is this mixing up the pixel block definition of sync vs the basic
> block definition (which has all the composite, green etc bits)?
The VESA spec seems to allow detailed modes to send sync signals in
different ways -- embedded with the analog signal, on one separate wire
or on two separate wires.
> Looks ok, but according to wikipedia hsync+ is 1<<1 and vsync+ is 1<<2
> instead. Other than that the #defines look ok (and I wouldn't trust
> wikipedia; iirc it had a few errors when I looked at it last).
Wikipedia is correct and my code was wrong. good catch!
keith.packard at intel.com
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