[Intel-gfx] [PATCH 1/2] drm: Fix EDID detailed timing misc flags decoding

Jesse Barnes jbarnes at virtuousgeek.org
Fri Jun 26 03:44:02 CEST 2009

On Thu, 25 Jun 2009 17:57:47 -0700
Keith Packard <keithp at keithp.com> wrote:

> On Thu, 2009-06-25 at 16:50 -0700, Jesse Barnes wrote:
> > Is this mixing up the pixel block definition of sync vs the basic
> > block definition (which has all the composite, green etc bits)?
> The VESA spec seems to allow detailed modes to send sync signals in
> different ways -- embedded with the analog signal, on one separate
> wire or on two separate wires.

Ok cool, I didn't have it in front of me so I wasn't sure of the
encoding in the detailed timing vs basic block section.

Jesse Barnes, Intel Open Source Technology Center

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