[Intel-gfx] [PATCH 4/4]Use best PLL timing values for G965 platform

[Ma Ling]

construct function to find precise parameters from internal spreadsheet table on G965 platform. 

Signed-off-by: Ma Ling <ling.ma at intel.com>
---
 src/i830_display.c |   68 ++++++++++++++++++++++++++++++++++++++++++++++++----
 1 files changed, 63 insertions(+), 5 deletions(-)

diff --git a/src/i830_display.c b/src/i830_display.c
index 968934f..50a3d69 100644
--- a/src/i830_display.c
+++ b/src/i830_display.c
@@ -345,6 +345,9 @@ static Bool
 intel_find_pll_i8xx_and_i9xx(intel_limit_t *, xf86CrtcPtr,
                              int, int, intel_clock_t *);
 static Bool
+intel_find_pll_g965(intel_limit_t *, xf86CrtcPtr,
+                    int, int, intel_clock_t *);
+static Bool
 intel_find_pll_g4x(intel_limit_t *, xf86CrtcPtr,
                    int, int, intel_clock_t *);
 
@@ -445,7 +448,7 @@ static const intel_limit_t intel_limits[] = {
         .p2  = { .dot_limit = G965_P2_SDVO_LIMIT,
                  .p2_slow = G965_P2_SDVO_SLOW,
                  .p2_fast = G965_P2_SDVO_FAST },
-        .find_pll = intel_find_pll_i8xx_and_i9xx,
+        .find_pll = intel_find_pll_g965,
     },
     {   /* INTEL_LIMIT_G965_DAC */
         .dot = { .min = G965_DOT_DAC_MIN,       .max = G965_DOT_DAC_MAX },
@@ -459,7 +462,7 @@ static const intel_limit_t intel_limits[] = {
         .p2  = { .dot_limit = G965_P2_DAC_LIMIT,
                  .p2_slow = G965_P2_DAC_SLOW,
                  .p2_fast = G965_P2_DAC_FAST },
-        .find_pll = intel_find_pll_i8xx_and_i9xx,
+        .find_pll = intel_find_pll_g965,
     },
     {   /* INTEL_LIMIT_G965_HDMI */
         .dot = { .min = G965_DOT_HDMI_MIN,	.max = G965_DOT_HDMI_MAX },
@@ -473,7 +476,7 @@ static const intel_limit_t intel_limits[] = {
         .p2  = { .dot_limit = G965_P2_HDMI_LIMIT,
                  .p2_slow = G965_P2_HDMI_SLOW,
                  .p2_fast = G965_P2_HDMI_FAST },
-        .find_pll = intel_find_pll_i8xx_and_i9xx,
+        .find_pll = intel_find_pll_g965,
     },
     {   /* INTEL_LIMIT_G965_SINGLE_LVDS */
         .dot = { .min = G965_DOT_SINGLE_LVDS_MIN,
@@ -495,7 +498,7 @@ static const intel_limit_t intel_limits[] = {
         .p2  = { .dot_limit = G965_P2_SINGLE_LVDS_LIMIT,
                  .p2_slow = G965_P2_SINGLE_LVDS_SLOW,
                  .p2_fast = G965_P2_SINGLE_LVDS_FAST },
-        .find_pll = intel_find_pll_i8xx_and_i9xx,
+        .find_pll = intel_find_pll_g965,
     },
     {   /* INTEL_LIMIT_G965_DUAL_LVDS */
         .dot = { .min = G965_DOT_DUAL_LVDS_MIN,
@@ -517,7 +520,7 @@ static const intel_limit_t intel_limits[] = {
         .p2  = { .dot_limit = G965_P2_DUAL_LVDS_LIMIT,
                  .p2_slow = G965_P2_DUAL_LVDS_SLOW,
                  .p2_fast = G965_P2_DUAL_LVDS_FAST },
-        .find_pll = intel_find_pll_i8xx_and_i9xx,
+        .find_pll = intel_find_pll_g965,
     },
     /* below parameter and function is for G4X Chipset Family*/
     {   /* INTEL_LIMIT_G4X_SDVO */
@@ -840,6 +843,61 @@ intel_find_pll_i8xx_and_i9xx(intel_limit_t * limit, xf86CrtcPtr crtc,
 }
 
 static Bool
+intel_find_pll_g965(intel_limit_t * limit, xf86CrtcPtr crtc,
+                   int target, int refclk, intel_clock_t *best_clock)
+{
+     ScrnInfoPtr pScrn = crtc->scrn;
+     I830Ptr pI830 = I830PTR(pScrn);
+     intel_clock_t clock;
+     Bool found = FALSE;
+     int err_most = target * 0.0048;
+
+     if (i830PipeHasType(crtc, I830_OUTPUT_LVDS)) {
+         /* For LVDS, if the panel is on, just rely on its current settings for
+          * dual-channel.  We haven't figured out how to reliably set up
+          * different single/dual channel state, if we even can.
+          */
+         if ((INREG(LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
+             clock.p2 = limit->p2.p2_fast;
+         else
+             clock.p2 = limit->p2.p2_slow;
+     } else {
+         if (target < limit->p2.dot_limit)
+             clock.p2 = limit->p2.p2_slow;
+         else
+             clock.p2 = limit->p2.p2_fast;
+     }
+
+     memset (best_clock, 0, sizeof (*best_clock));
+
+     /* based on hardware requirement prefer smaller n to precision */
+     for (clock.n = limit->n.min; clock.n <= limit->n.max; clock.n++) {
+         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
+             for (clock.m2 = limit->m2.min;
+                  clock.m2 <= limit->m2.max; clock.m2++) {
+                 for (clock.p1 = limit->p1.min;
+                      clock.p1 <= limit->p1.max; clock.p1++) {
+                     int this_err;
+
+                     intel_clock (pI830, refclk, &clock);
+
+                     if (!i830PllIsValid(crtc, &clock))
+                         continue;
+
+                     this_err = abs(clock.dot - target) ;
+                     if (this_err < err_most) {
+                         *best_clock = clock;
+                         err_most = this_err;
+                         found = TRUE;
+                     }
+                 }
+             }
+         }
+     }
+     return found;
+}
+
+static Bool
 intel_find_pll_g4x(intel_limit_t * limit, xf86CrtcPtr crtc,
                    int target, int refclk, intel_clock_t *best_clock)
 {
-- 
1.5.4.4