[Intel-gfx] [PATCH 3/4]Define documented PLL timing limits for G965 platform
Eric Anholt
eric at anholt.net
Fri Mar 20 22:28:00 CET 2009
On Fri, 2009-03-13 at 13:24 +0800, Ma Ling wrote:
> These timings on G965 platform were specified by internal spreadsheet from the chipset group.
Do we have bugs that this is fixing? Wondering which tree it's
targeting. Also, will need rebasing on top of drm-intel-next or
for-linus once I push the current stuff out.
> Signed-off-by: Ma Ling <ling.ma at intel.com>
> ---
> src/i830_display.c | 222 +++++++++++++++++++++++++++++++++++++++++++++++++++-
> 1 files changed, 218 insertions(+), 4 deletions(-)
>
> diff --git a/src/i830_display.c b/src/i830_display.c
> index af1e96f..968934f 100644
> --- a/src/i830_display.c
> +++ b/src/i830_display.c
> @@ -156,10 +156,112 @@ struct intel_limit {
> #define INTEL_LIMIT_I9XX_LVDS 3
> #define INTEL_LIMIT_IGD_SDVO_DAC 4
> #define INTEL_LIMIT_IGD_LVDS 5
> -#define INTEL_LIMIT_G4X_SDVO 6
> -#define INTEL_LIMIT_G4X_HDMI_DAC 7
> -#define INTEL_LIMIT_G4X_SINGLE_LVDS 8
> -#define INTEL_LIMIT_G4X_DUAL_LVDS 9
> +#define INTEL_LIMIT_G965_SDVO 6
> +#define INTEL_LIMIT_G965_DAC 7
> +#define INTEL_LIMIT_G965_HDMI 8
> +#define INTEL_LIMIT_G965_SINGLE_LVDS 9
> +#define INTEL_LIMIT_G965_DUAL_LVDS 10
> +#define INTEL_LIMIT_G4X_SDVO 11
> +#define INTEL_LIMIT_G4X_HDMI_DAC 12
> +#define INTEL_LIMIT_G4X_SINGLE_LVDS 13
> +#define INTEL_LIMIT_G4X_DUAL_LVDS 14
OK, we're going to need to make this an enum. This is getting silly.
> +/*The parameter is for SDVO on G965 platform*/
> +#define G965_VCO_MIN 1600000
> +#define G965_VCO_MAX 3200000
> +#define G965_DOT_SDVO_MIN 25000
> +#define G965_DOT_SDVO_MAX 270000
> +#define G965_N_SDVO_MIN 1
> +#define G965_N_SDVO_MAX 5
> +#define G965_M_SDVO_MIN 90
> +#define G965_M_SDVO_MAX 130
> +#define G965_M1_SDVO_MIN 14
> +#define G965_M1_SDVO_MAX 22
> +#define G965_M2_SDVO_MIN 5
> +#define G965_M2_SDVO_MAX 9
> +#define G965_P_SDVO_MIN 10
> +#define G965_P_SDVO_MAX 30
> +#define G965_P1_SDVO_MIN 1
> +#define G965_P1_SDVO_MAX 3
> +#define G965_P2_SDVO_SLOW 10
> +#define G965_P2_SDVO_FAST 10
> +#define G965_P2_SDVO_LIMIT 270000
> +
> +/*The parameter is for DAC on G965 platform*/
> +#define G965_DOT_DAC_MIN 20000
> +#define G965_DOT_DAC_MAX 400000
> +#define G965_N_DAC_MIN 1
> +#define G965_N_DAC_MAX 5
> +#define G965_M_DAC_MIN 90
> +#define G965_M_DAC_MAX 130
> +#define G965_M1_DAC_MIN 14
> +#define G965_M1_DAC_MAX 22
> +#define G965_M2_DAC_MIN 5
> +#define G965_M2_DAC_MAX 9
> +#define G965_P_DAC_MIN 5
> +#define G965_P_DAC_MAX 30
> +#define G965_P1_DAC_MIN 1
> +#define G965_P1_DAC_MAX 3
> +#define G965_P2_DAC_SLOW 10
> +#define G965_P2_DAC_FAST 5
> +#define G965_P2_DAC_LIMIT 270000
> +
> +/*The parameter is for HDMI on G965 platform*/
> +#define G965_DOT_HDMI_MIN 20000
> +#define G965_DOT_HDMI_MAX 165000
> +#define G965_N_HDMI_MIN 1
> +#define G965_N_HDMI_MAX 5
> +#define G965_M_HDMI_MIN 90
> +#define G965_M_HDMI_MAX 130
> +#define G965_M1_HDMI_MIN 14
> +#define G965_M1_HDMI_MAX 22
> +#define G965_M2_HDMI_MIN 5
> +#define G965_M2_HDMI_MAX 9
> +#define G965_P_HDMI_MIN 10
> +#define G965_P_HDMI_MAX 80
> +#define G965_P1_HDMI_MIN 1
> +#define G965_P1_HDMI_MAX 8
> +#define G965_P2_HDMI_SLOW 10
> +#define G965_P2_HDMI_FAST 10
> +#define G965_P2_HDMI_LIMIT 165000
> +
> +/*The parameter is for SINGLE_LVDS on G965 platform*/
> +#define G965_DOT_SINGLE_LVDS_MIN 20000
> +#define G965_DOT_SINGLE_LVDS_MAX 115000
> +#define G965_N_SINGLE_LVDS_MIN 1
> +#define G965_N_SINGLE_LVDS_MAX 5
> +#define G965_M_SINGLE_LVDS_MIN 90
> +#define G965_M_SINGLE_LVDS_MAX 128
> +#define G965_M1_SINGLE_LVDS_MIN 14
> +#define G965_M1_SINGLE_LVDS_MAX 22
> +#define G965_M2_SINGLE_LVDS_MIN 5
> +#define G965_M2_SINGLE_LVDS_MAX 9
> +#define G965_P_SINGLE_LVDS_MIN 14
> +#define G965_P_SINGLE_LVDS_MAX 112
> +#define G965_P1_SINGLE_LVDS_MIN 1
> +#define G965_P1_SINGLE_LVDS_MAX 8
> +#define G965_P2_SINGLE_LVDS_SLOW 14
> +#define G965_P2_SINGLE_LVDS_FAST 14
> +#define G965_P2_SINGLE_LVDS_LIMIT 0
> +
> +/*The parameter is for DUAL_LVDS on G965 platform*/
> +#define G965_DOT_DUAL_LVDS_MIN 80000
> +#define G965_DOT_DUAL_LVDS_MAX 224000
> +#define G965_N_DUAL_LVDS_MIN 1
> +#define G965_N_DUAL_LVDS_MAX 5
> +#define G965_M_DUAL_LVDS_MIN 90
> +#define G965_M_DUAL_LVDS_MAX 130
> +#define G965_M1_DUAL_LVDS_MIN 14
> +#define G965_M1_DUAL_LVDS_MAX 22
> +#define G965_M2_DUAL_LVDS_MIN 5
> +#define G965_M2_DUAL_LVDS_MAX 9
> +#define G965_P_DUAL_LVDS_MIN 14
> +#define G965_P_DUAL_LVDS_MAX 35
> +#define G965_P1_DUAL_LVDS_MIN 2
> +#define G965_P1_DUAL_LVDS_MAX 5
> +#define G965_P2_DUAL_LVDS_SLOW 7
> +#define G965_P2_DUAL_LVDS_FAST 7
> +#define G965_P2_DUAL_LVDS_LIMIT 0
>
> /*The parameter is for SDVO on G4x platform*/
> #define G4X_VCO_MIN 1750000
> @@ -330,6 +432,93 @@ static const intel_limit_t intel_limits[] = {
> .find_pll = intel_find_pll_i8xx_and_i9xx,
> },
>
> + /* below parameter and function is for G965 Chipset Family*/
> + { /* INTEL_LIMIT_G965_SDVO */
> + .dot = { .min = G965_DOT_SDVO_MIN, .max = G965_DOT_SDVO_MAX },
> + .vco = { .min = G965_VCO_MIN, .max = G965_VCO_MAX},
> + .n = { .min = G965_N_SDVO_MIN, .max = G965_N_SDVO_MAX },
> + .m = { .min = G965_M_SDVO_MIN, .max = G965_M_SDVO_MAX },
> + .m1 = { .min = G965_M1_SDVO_MIN, .max = G965_M1_SDVO_MAX },
> + .m2 = { .min = G965_M2_SDVO_MIN, .max = G965_M2_SDVO_MAX },
> + .p = { .min = G965_P_SDVO_MIN, .max = G965_P_SDVO_MAX },
> + .p1 = { .min = G965_P1_SDVO_MIN, .max = G965_P1_SDVO_MAX},
> + .p2 = { .dot_limit = G965_P2_SDVO_LIMIT,
> + .p2_slow = G965_P2_SDVO_SLOW,
> + .p2_fast = G965_P2_SDVO_FAST },
> + .find_pll = intel_find_pll_i8xx_and_i9xx,
> + },
> + { /* INTEL_LIMIT_G965_DAC */
> + .dot = { .min = G965_DOT_DAC_MIN, .max = G965_DOT_DAC_MAX },
> + .vco = { .min = G965_VCO_MIN, .max = G965_VCO_MAX},
> + .n = { .min = G965_N_DAC_MIN, .max = G965_N_DAC_MAX },
> + .m = { .min = G965_M_DAC_MIN, .max = G965_M_DAC_MAX },
> + .m1 = { .min = G965_M1_DAC_MIN, .max = G965_M1_DAC_MAX },
> + .m2 = { .min = G965_M2_DAC_MIN, .max = G965_M2_DAC_MAX },
> + .p = { .min = G965_P_DAC_MIN, .max = G965_P_DAC_MAX },
> + .p1 = { .min = G965_P1_DAC_MIN, .max = G965_P1_DAC_MAX},
> + .p2 = { .dot_limit = G965_P2_DAC_LIMIT,
> + .p2_slow = G965_P2_DAC_SLOW,
> + .p2_fast = G965_P2_DAC_FAST },
> + .find_pll = intel_find_pll_i8xx_and_i9xx,
> + },
> + { /* INTEL_LIMIT_G965_HDMI */
> + .dot = { .min = G965_DOT_HDMI_MIN, .max = G965_DOT_HDMI_MAX },
> + .vco = { .min = G965_VCO_MIN, .max = G965_VCO_MAX},
> + .n = { .min = G965_N_HDMI_MIN, .max = G965_N_HDMI_MAX },
> + .m = { .min = G965_M_HDMI_MIN, .max = G965_M_HDMI_MAX },
> + .m1 = { .min = G965_M1_HDMI_MIN, .max = G965_M1_HDMI_MAX },
> + .m2 = { .min = G965_M2_HDMI_MIN, .max = G965_M2_HDMI_MAX },
> + .p = { .min = G965_P_HDMI_MIN, .max = G965_P_HDMI_MAX },
> + .p1 = { .min = G965_P1_HDMI_MIN, .max = G965_P1_HDMI_MAX},
> + .p2 = { .dot_limit = G965_P2_HDMI_LIMIT,
> + .p2_slow = G965_P2_HDMI_SLOW,
> + .p2_fast = G965_P2_HDMI_FAST },
> + .find_pll = intel_find_pll_i8xx_and_i9xx,
> + },
> + { /* INTEL_LIMIT_G965_SINGLE_LVDS */
> + .dot = { .min = G965_DOT_SINGLE_LVDS_MIN,
> + .max = G965_DOT_SINGLE_LVDS_MAX },
> + .vco = { .min = G965_VCO_MIN,
> + .max = G965_VCO_MAX },
> + .n = { .min = G965_N_SINGLE_LVDS_MIN,
> + .max = G965_N_SINGLE_LVDS_MAX },
> + .m = { .min = G965_M_SINGLE_LVDS_MIN,
> + .max = G965_M_SINGLE_LVDS_MAX },
> + .m1 = { .min = G965_M1_SINGLE_LVDS_MIN,
> + .max = G965_M1_SINGLE_LVDS_MAX },
> + .m2 = { .min = G965_M2_SINGLE_LVDS_MIN,
> + .max = G965_M2_SINGLE_LVDS_MAX },
> + .p = { .min = G965_P_SINGLE_LVDS_MIN,
> + .max = G965_P_SINGLE_LVDS_MAX },
> + .p1 = { .min = G965_P1_SINGLE_LVDS_MIN,
> + .max = G965_P1_SINGLE_LVDS_MAX },
> + .p2 = { .dot_limit = G965_P2_SINGLE_LVDS_LIMIT,
> + .p2_slow = G965_P2_SINGLE_LVDS_SLOW,
> + .p2_fast = G965_P2_SINGLE_LVDS_FAST },
> + .find_pll = intel_find_pll_i8xx_and_i9xx,
> + },
> + { /* INTEL_LIMIT_G965_DUAL_LVDS */
> + .dot = { .min = G965_DOT_DUAL_LVDS_MIN,
> + .max = G965_DOT_DUAL_LVDS_MAX },
> + .vco = { .min = G965_VCO_MIN,
> + .max = G965_VCO_MAX},
> + .n = { .min = G965_N_DUAL_LVDS_MIN,
> + .max = G965_N_DUAL_LVDS_MAX },
> + .m = { .min = G965_M_DUAL_LVDS_MIN,
> + .max = G965_M_DUAL_LVDS_MAX },
> + .m1 = { .min = G965_M1_DUAL_LVDS_MIN,
> + .max = G965_M1_DUAL_LVDS_MAX },
> + .m2 = { .min = G965_M2_DUAL_LVDS_MIN,
> + .max = G965_M2_DUAL_LVDS_MAX },
> + .p = { .min = G965_P_DUAL_LVDS_MIN,
> + .max = G965_P_DUAL_LVDS_MAX },
> + .p1 = { .min = G965_P1_DUAL_LVDS_MIN,
> + .max = G965_P1_DUAL_LVDS_MAX},
> + .p2 = { .dot_limit = G965_P2_DUAL_LVDS_LIMIT,
> + .p2_slow = G965_P2_DUAL_LVDS_SLOW,
> + .p2_fast = G965_P2_DUAL_LVDS_FAST },
> + .find_pll = intel_find_pll_i8xx_and_i9xx,
> + },
> /* below parameter and function is for G4X Chipset Family*/
> { /* INTEL_LIMIT_G4X_SDVO */
> .dot = { .min = G4X_DOT_SDVO_MIN, .max = G4X_DOT_SDVO_MAX },
> @@ -405,6 +594,29 @@ static const intel_limit_t intel_limits[] = {
> },
> };
>
> +static const intel_limit_t *intel_limit_g965 (xf86CrtcPtr crtc)
> +{
> + ScrnInfoPtr pScrn = crtc->scrn;
> + I830Ptr pI830 = I830PTR(pScrn);
> + const intel_limit_t *limit;
> +
> + if (i830PipeHasType (crtc, I830_OUTPUT_LVDS)) {
> + if ((INREG(LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP) {
> + /* LVDS with dual channel */
> + limit = &intel_limits[INTEL_LIMIT_G965_DUAL_LVDS];
> + } else /* LVDS with single channel */
> + limit = &intel_limits[INTEL_LIMIT_G965_SINGLE_LVDS];
> + } else if (i830PipeHasType (crtc, I830_OUTPUT_ANALOG)) {
> + limit = &intel_limits[INTEL_LIMIT_G965_DAC];
> + } else if (i830PipeHasType (crtc, I830_OUTPUT_HDMI)) {
> + limit = &intel_limits[INTEL_LIMIT_G965_HDMI];
> + } else if (i830PipeHasType (crtc, I830_OUTPUT_SDVO)) {
> + limit = &intel_limits[INTEL_LIMIT_G965_SDVO];
> + } else /* The option is for other outputs */
> + limit = &intel_limits[INTEL_LIMIT_I9XX_SDVO_DAC];
> + return limit;
> + }
> +
> static const intel_limit_t *intel_limit_g4x (xf86CrtcPtr crtc)
> {
> ScrnInfoPtr pScrn = crtc->scrn;
> @@ -435,6 +647,8 @@ static const intel_limit_t *intel_limit (xf86CrtcPtr crtc)
>
> if (IS_G4X(pI830)) {
> limit = intel_limit_g4x(crtc);
> + } else if (IS_I965G(pI830)) {
> + limit = intel_limit_g965(crtc);
> } else if (IS_I9XX(pI830) && !IS_IGD(pI830)) {
> if (i830PipeHasType (crtc, I830_OUTPUT_LVDS))
> limit = &intel_limits[INTEL_LIMIT_I9XX_LVDS];
--
Eric Anholt
eric at anholt.net eric.anholt at intel.com
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 197 bytes
Desc: This is a digitally signed message part
URL: <http://lists.freedesktop.org/archives/intel-gfx/attachments/20090320/2678f1fc/attachment.sig>
More information about the Intel-gfx
mailing list