[Intel-gfx] [PATCH] add get_vblank_counter function for GM45
Robert Noland
rnoland at 2hip.net
Sat May 2 18:32:02 CEST 2009
On Fri, 2009-02-06 at 10:22 -0800, Jesse Barnes wrote:
> As discussed in the long thread about vblank related timeouts, it turns out
> GM45 has different frame count registers than previous chips. This patch
> adds support for them, which prevents us from waiting on really stale
> sequence values in drm_wait_vblank (which rather than returning immediately
> ends up timing out or getting interrupted).
I'm not seeing this patch in drm-next... It looks like this register
should be used for all G4X chips, not just GM45. The counter on my G45
(2E22) was counting really fast using the old method. Using this
register the values seem correct. The docs appear to hold up this
argument as well I think (devELK).
Running gears synced to vblank was working since vblanks just stay on.
If vblanks are being switched on and off, (rotating the cube in compiz)
I was seeing really bad behavior after a few minutes.
Also note that in this case max_vblank_count is 32 bits, not 24. I'm
setting that value at the same time that I set the function now.
robert.
> Signed-off-by: Jesse Barnes <jbarnes at virtuousgeek.org>
>
> diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> index 0ded483..81f1cff 100644
> --- a/drivers/gpu/drm/i915/i915_dma.c
> +++ b/drivers/gpu/drm/i915/i915_dma.c
> @@ -1112,6 +1112,10 @@ int i915_driver_load(struct drm_device *dev, unsigned
> long flags)
> dev_priv->has_gem = 1;
> #endif
>
> + dev->driver->get_vblank_counter = i915_get_vblank_counter;
> + if (IS_GM45(dev))
> + dev->driver->get_vblank_counter = gm45_get_vblank_counter;
> +
> i915_gem_load(dev);
>
> /* Init HWS */
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index f8b3df0..aac12ee 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -112,7 +112,6 @@ static struct drm_driver driver = {
> .suspend = i915_suspend,
> .resume = i915_resume,
> .device_is_agp = i915_driver_device_is_agp,
> - .get_vblank_counter = i915_get_vblank_counter,
> .enable_vblank = i915_enable_vblank,
> .disable_vblank = i915_disable_vblank,
> .irq_preinstall = i915_driver_irq_preinstall,
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index a70bf77..7325363 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -535,6 +535,7 @@ extern int i915_vblank_pipe_get(struct drm_device *dev,
> void *data,
> extern int i915_enable_vblank(struct drm_device *dev, int crtc);
> extern void i915_disable_vblank(struct drm_device *dev, int crtc);
> extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
> +extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc);
> extern int i915_vblank_swap(struct drm_device *dev, void *data,
> struct drm_file *file_priv);
> extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask);
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 6290219..548ff2c 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -174,6 +174,19 @@ u32 i915_get_vblank_counter(struct drm_device *dev, int
> pipe)
> return count;
> }
>
> +u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
> +{
> + drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
> + int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45;
> +
> + if (!i915_pipe_enabled(dev, pipe)) {
> + DRM_ERROR("trying to get vblank count for disabled pipe %d\n", pipe);
> + return 0;
> + }
> +
> + return I915_READ(reg);
> +}
> +
> irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
> {
> struct drm_device *dev = (struct drm_device *) arg;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 928e004..9d6539a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1371,6 +1371,9 @@
> #define PIPE_FRAME_LOW_SHIFT 24
> #define PIPE_PIXEL_MASK 0x00ffffff
> #define PIPE_PIXEL_SHIFT 0
> +/* GM45+ just has to be different */
> +#define PIPEA_FRMCOUNT_GM45 0x70040
> +#define PIPEA_FLIPCOUNT_GM45 0x70044
>
> /* Cursor A & B regs */
> #define CURACNTR 0x70080
> @@ -1439,6 +1442,9 @@
> #define PIPEBSTAT 0x71024
> #define PIPEBFRAMEHIGH 0x71040
> #define PIPEBFRAMEPIXEL 0x71044
> +#define PIPEB_FRMCOUNT_GM45 0x71040
> +#define PIPEB_FLIPCOUNT_GM45 0x71044
> +
>
> /* Display B control */
> #define DSPBCNTR 0x71180
>
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--
Robert Noland <rnoland at 2hip.net>
2Hip Networks
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