[Intel-gfx] [PATCH] i915: apply G45 vblank count code to all G4x chips and fix max_frame_count

[Jesse Barnes]

On Tue, 05 May 2009 13:50:57 -0500
Robert Noland <rnoland at 2hip.net> wrote:

> On Tue, 2009-05-05 at 10:44 -0700, Jesse Barnes wrote:
> > On Sat, 02 May 2009 11:32:02 -0500
> > Robert Noland <rnoland at 2hip.net> wrote:
> > 
> > > On Fri, 2009-02-06 at 10:22 -0800, Jesse Barnes wrote:
> > > > As discussed in the long thread about vblank related timeouts,
> > > > it turns out GM45 has different frame count registers than
> > > > previous chips.  This patch adds support for them, which
> > > > prevents us from waiting on really stale sequence values in
> > > > drm_wait_vblank (which rather than returning immediately ends
> > > > up timing out or getting interrupted).
> > > 
> > > I'm not seeing this patch in drm-next... It looks like this
> > > register should be used for all G4X chips, not just GM45.  The
> > > counter on my G45 (2E22) was counting really fast using the old
> > > method.  Using this register the values seem correct.  The docs
> > > appear to hold up this argument as well I think (devELK).
> > > 
> > > Running gears synced to vblank was working since vblanks just
> > > stay on. If vblanks are being switched on and off, (rotating the
> > > cube in compiz) I was seeing really bad behavior after a few
> > > minutes.
> > > 
> > > Also note that in this case max_vblank_count is 32 bits, not 24.
> > > I'm setting that value at the same time that I set the function
> > > now.
> > 
> > Yes it should be for G4x.  Patch below.
> 
> You aren't dealing with the hardware counter being 32 bits now, so
> once you cross the 24 bit boundary the calculations in
> drm_update_vblank_counter() will be wrong.

Oh yeah forgot to update the count.

--

All G4x and newer chips use the new style frame count register, with a
full 32 bit frame count.  Update the code to reflect this.

Signed-off-by: Jesse Barnes <jbarnes at virtuousgeek.org>

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 051134c..6354c31 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1153,8 +1153,11 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
 #endif
 
 	dev->driver->get_vblank_counter = i915_get_vblank_counter;
-	if (IS_GM45(dev))
+	dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
+	if (IS_G4X(dev)) {
+		dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
 		dev->driver->get_vblank_counter = gm45_get_vblank_counter;
+	}
 
 	i915_gem_load(dev);
 
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 98bb4c8..8ee0969 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -572,8 +572,6 @@ int i915_driver_irq_postinstall(struct drm_device *dev)
 
 	dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
 
-	dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
-
 	/* Unmask the interrupts that we always want on. */
 	dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX;