[Intel-gfx] [PATCH ] drm/i915: assign short type value without a cast

[Simon Farnsworth]

Ma Ling wrote:
> On some RISC platform i.e. Sparc, ARM, they will use Load word instruction to access memory.
> The Load word instruction require address must be 2 bytes aligned. the System will crash
> because address of (base + index) may be not 2bytes aligned.
> The patch intends to avoid the case. 
> 
> Signed-off-by: Ma Ling <ling.ma at intel.com>
> ---
>  drivers/gpu/drm/i915/intel_bios.c |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
> index fc28e2b..cf2bdc6 100644
> --- a/drivers/gpu/drm/i915/intel_bios.c
> +++ b/drivers/gpu/drm/i915/intel_bios.c
> @@ -47,7 +47,7 @@ find_section(struct bdb_header *bdb, int section_id)
>  	while (index < total) {
>  		current_id = *(base + index);
>  		index++;
> -		current_size = *((u16 *)(base + index));
> +		current_size = base[index] | base[index + 1] << 8;

Rather than open-code this, and relying on the compiler spotting what
you're doing, why not use the get_unaligned macros from asm/unaligned.h?

Leaves you with something like:
                current_size = get_unaligned_le((u16 *)(base + index));

Otherwise, you're relying on the RISC chip having the correct endianness
as well as correct alignment; additionally, arch maintainers *should*
ensure that get_unaligned is as fast as possible for that architecture.

>  		index += 2;
>  		if (current_id == section_id)
>  			return base + index;


-- 
Simon Farnsworth