[Intel-gfx] Fwd: [PATCH 2/3] Get the LVDS panel limit and check whether the given modeline is valid
Alexander E. Patrakov
patrakov at gmail.com
Thu May 21 09:31:53 CEST 2009
Oops, forgot the list.
---------- Forwarded message ----------
From: Alexander E. Patrakov <patrakov at gmail.com>
Date: 2009/5/21
Subject: Re: [Intel-gfx] [PATCH 2/3] Get the LVDS panel limit and
check whether the given modeline is valid
To: yakui_zhao <yakui.zhao at intel.com>
2009/5/21 yakui_zhao <yakui.zhao at intel.com>:
>
> When the connector type is LVDS, it will traverse the mode list returned by KMS kernel to
> get the LVDS panel limit.
> Then it will use the panel limit to check whether the given modeline is valid.
> If the given modeline exceeds the LVDS panel limit, it will be invalid.
>
> Signed-off-by: Zhao Yakui <yakui.zhao at intel.com>
Untested, but I don't think this will work right for my laptop
(Fujitsu Siemens LIFEBOOK S6410). With linux-2.6.30-rc4, KMS and
xf86-video-intel-2.7.0 and xorg-server-1.6.1, I get (note the
completely bogus 1360x768 mode for the panel - where did it come
from?):
aep at aep:~$ xrandr --verbose
Screen 0: minimum 320 x 200, current 1280 x 1024, maximum 8192 x 8192
VGA1 connected 1280x1024+0+0 (0x3e) normal (normal left inverted right
x axis y axis) 376mm x 301mm
Identifier: 0x3b
Timestamp: 48521
Subpixel: unknown
Clones: DVI1
CRTC: 0
CRTCs: 0 1
Transform: 1.000000 0.000000 0.000000
0.000000 1.000000 0.000000
0.000000 0.000000 1.000000
filter:
EDID_DATA:
00ffffffffffff0038a3626601010101
071201030e261e78eacb05a3584c9b25
135054bfef80714f8140818001010101
010101010101302a009851002a403070
1300782d1100001e000000fd00384b1f
510e000a202020202020000000fc004c
4344313937304e580a202020000000ff
00383242353234303259420a2020000d
1280x1024 (0x3e) 108.0MHz +HSync +VSync *current +preferred
h: width 1280 start 1328 end 1440 total 1688 skew 0 clock 64.0KHz
v: height 1024 start 1025 end 1028 total 1066 clock 60.0Hz
1280x1024 (0x3f) 135.0MHz +HSync +VSync
h: width 1280 start 1296 end 1440 total 1688 skew 0 clock 80.0KHz
v: height 1024 start 1025 end 1028 total 1066 clock 75.0Hz
1152x864 (0x40) 108.0MHz +HSync +VSync
h: width 1152 start 1216 end 1344 total 1600 skew 0 clock 67.5KHz
v: height 864 start 865 end 868 total 900 clock 75.0Hz
1024x768 (0x41) 78.8MHz +HSync +VSync
h: width 1024 start 1040 end 1136 total 1312 skew 0 clock 60.1KHz
v: height 768 start 769 end 772 total 800 clock 75.1Hz
1024x768 (0x42) 75.0MHz -HSync -VSync
h: width 1024 start 1048 end 1184 total 1328 skew 0 clock 56.5KHz
v: height 768 start 771 end 777 total 806 clock 70.1Hz
1024x768 (0x43) 65.0MHz -HSync -VSync
h: width 1024 start 1048 end 1184 total 1344 skew 0 clock 48.4KHz
v: height 768 start 771 end 777 total 806 clock 60.0Hz
832x624 (0x44) 57.3MHz -HSync -VSync
h: width 832 start 864 end 928 total 1152 skew 0 clock 49.7KHz
v: height 624 start 625 end 628 total 667 clock 74.6Hz
800x600 (0x45) 50.0MHz +HSync +VSync
h: width 800 start 856 end 976 total 1040 skew 0 clock 48.1KHz
v: height 600 start 637 end 643 total 666 clock 72.2Hz
800x600 (0x46) 49.5MHz +HSync +VSync
h: width 800 start 816 end 896 total 1056 skew 0 clock 46.9KHz
v: height 600 start 601 end 604 total 625 clock 75.0Hz
800x600 (0x47) 40.0MHz +HSync +VSync
h: width 800 start 840 end 968 total 1056 skew 0 clock 37.9KHz
v: height 600 start 601 end 605 total 628 clock 60.3Hz
800x600 (0x48) 36.0MHz +HSync +VSync
h: width 800 start 824 end 896 total 1024 skew 0 clock 35.2KHz
v: height 600 start 601 end 603 total 625 clock 56.2Hz
640x480 (0x49) 31.5MHz -HSync -VSync
h: width 640 start 664 end 704 total 832 skew 0 clock 37.9KHz
v: height 480 start 489 end 491 total 520 clock 72.8Hz
640x480 (0x4a) 31.5MHz -HSync -VSync
h: width 640 start 656 end 720 total 840 skew 0 clock 37.5KHz
v: height 480 start 481 end 484 total 500 clock 75.0Hz
640x480 (0x4b) 30.2MHz -HSync -VSync
h: width 640 start 704 end 768 total 864 skew 0 clock 35.0KHz
v: height 480 start 483 end 486 total 525 clock 66.7Hz
640x480 (0x4c) 25.2MHz -HSync -VSync
h: width 640 start 656 end 752 total 800 skew 0 clock 31.5KHz
v: height 480 start 490 end 492 total 525 clock 60.0Hz
720x400 (0x4d) 28.3MHz -HSync +VSync
h: width 720 start 738 end 846 total 900 skew 0 clock 31.5KHz
v: height 400 start 412 end 414 total 449 clock 70.1Hz
LVDS1 connected (normal left inverted right x axis y axis)
Identifier: 0x3c
Timestamp: 48521
Subpixel: unknown
Clones:
CRTCs: 1
Transform: 1.000000 0.000000 0.000000
0.000000 1.000000 0.000000
0.000000 0.000000 1.000000
filter:
1280x800 (0x4e) 83.8MHz +preferred
h: width 1280 start 1352 end 1480 total 1680 skew 0 clock 49.9KHz
v: height 800 start 803 end 809 total 831 clock 60.0Hz
1360x768 (0x4f) 84.8MHz -HSync +VSync
h: width 1360 start 1432 end 1568 total 1776 skew 0 clock 47.7KHz
v: height 768 start 771 end 781 total 798 clock 59.8Hz
1024x768 (0x43) 65.0MHz -HSync -VSync
h: width 1024 start 1048 end 1184 total 1344 skew 0 clock 48.4KHz
v: height 768 start 771 end 777 total 806 clock 60.0Hz
800x600 (0x47) 40.0MHz +HSync +VSync
h: width 800 start 840 end 968 total 1056 skew 0 clock 37.9KHz
v: height 600 start 601 end 605 total 628 clock 60.3Hz
640x480 (0x50) 25.2MHz -HSync -VSync
h: width 640 start 656 end 752 total 800 skew 0 clock 31.5KHz
v: height 480 start 490 end 492 total 525 clock 59.9Hz
DVI1 disconnected (normal left inverted right x axis y axis)
Identifier: 0x3d
Timestamp: 48521
Subpixel: unknown
Clones: VGA1
CRTCs: 0 1
Transform: 1.000000 0.000000 0.000000
0.000000 1.000000 0.000000
0.000000 0.000000 1.000000
filter:
> ---
> src/drmmode_display.c | 38 ++++++++++++++++++++++++++++++++++++++
> 1 file changed, 38 insertions(+)
>
> Index: xf86_video_intel/src/drmmode_display.c
> ===================================================================
> --- xf86_video_intel.orig/src/drmmode_display.c 2009-05-21 11:39:38.000000000 +0800
> +++ xf86_video_intel/src/drmmode_display.c 2009-05-21 11:39:45.000000000 +0800
> @@ -471,6 +471,21 @@
> static Bool
> drmmode_output_mode_valid(xf86OutputPtr output, DisplayModePtr pModes)
> {
> + drmmode_output_private_ptr drmmode_output = output->driver_private;
> + drmModeConnectorPtr koutput = drmmode_output->mode_output;
> + struct fixed_panel_lvds *p_lvds = drmmode_output->private_data;
> +
> + /*
> + * If the connector type is LVDS, we will use the panel limit to
> + * verfiy whether the mode is valid.
> + */
> + if ((koutput->connector_type == DRM_MODE_CONNECTOR_LVDS) && p_lvds) {
> + if (pModes->HDisplay > p_lvds->hdisplay ||
> + pModes->VDisplay > p_lvds->vdisplay)
> + return MODE_PANEL;
> + else
> + return MODE_OK;
> + }
> return MODE_OK;
> }
>
> @@ -483,6 +498,8 @@
> int i;
> DisplayModePtr Modes = NULL, Mode;
> drmModePropertyPtr props;
> + struct fixed_panel_lvds *p_lvds;
> + drmModeModeInfo *mode_ptr;
>
> /* look for an EDID property */
> for (i = 0; i < koutput->count_props; i++) {
> @@ -518,6 +535,27 @@
> Modes = xf86ModesAdd(Modes, Mode);
>
> }
> + p_lvds = drmmode_output->private_data;
> + /*
> + * If the connector type is LVDS, we will traverse the kernel mode to
> + * get the panel limit.
> + * If it is incorrect, please fix me.
> + */
> + if ((koutput->connector_type == DRM_MODE_CONNECTOR_LVDS) && p_lvds) {
> + p_lvds->hdisplay = 0;
> + p_lvds->vdisplay = 0;
> + for (i = 0; i < koutput->count_modes; i++) {
> + mode_ptr = &koutput->modes[i];
> + if ((mode_ptr->hdisplay >= p_lvds->hdisplay) &&
> + (mode_ptr->vdisplay >= p_lvds->vdisplay)) {
> + p_lvds->hdisplay = mode_ptr->hdisplay;
> + p_lvds->vdisplay = mode_ptr->vdisplay;
So here, if I read the code correctly, it (depending on the mode
order) may think that my panel is either 1280x800 (right) or 1360x768.
> + }
> + }
> + if (!p_lvds->hdisplay || !p_lvds->vdisplay)
> + xf86DrvMsg(output->scrn->scrnIndex, X_ERROR,
> + "Incorrect KMS mode.\n");
> + }
> return Modes;
> }
--
Alexander E. Patrakov
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