[Intel-gfx] [PATCH 1/2] drm/i915: Update the IER interrupt register when enable irq on Ironlake

[yakui.zhao at intel.com]

From: Zhao Yakui <yakui.zhao at intel.com>

Update the IER interrupt registe when we enable display/graphics irq on the
Ironlake. Otherwise the corresponding interrupt bit is not enabled.

Signed-off-by: Zhao Yakui <yakui.zhao at intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h |    2 ++
 drivers/gpu/drm/i915/i915_irq.c |   12 ++++++++++++
 2 files changed, 14 insertions(+), 0 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9f35883..ddfd906 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -695,6 +695,8 @@ extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc);
 extern int i915_vblank_swap(struct drm_device *dev, void *data,
 			    struct drm_file *file_priv);
 extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask);
+extern void igdng_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask);
+extern void igdng_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask);
 
 void
 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 0887581..e8031b8 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -67,6 +67,9 @@ igdng_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
 		dev_priv->gt_irq_mask_reg &= ~mask;
 		I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
 		(void) I915_READ(GTIMR);
+		dev_priv->gt_irq_enable_reg |= mask;
+		I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg);
+		(void) I915_READ(GTIER);
 	}
 }
 
@@ -77,6 +80,9 @@ igdng_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
 		dev_priv->gt_irq_mask_reg |= mask;
 		I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
 		(void) I915_READ(GTIMR);
+		dev_priv->gt_irq_enable_reg &= ~mask;
+		I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg);
+		(void) I915_READ(GTIER);
 	}
 }
 
@@ -88,6 +94,9 @@ igdng_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
 		dev_priv->irq_mask_reg &= ~mask;
 		I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
 		(void) I915_READ(DEIMR);
+		dev_priv->de_irq_enable_reg |= mask;
+		I915_WRITE(DEIER, dev_priv->de_irq_enable_reg);
+		(void) I915_READ(DEIER);
 	}
 }
 
@@ -98,6 +107,9 @@ igdng_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
 		dev_priv->irq_mask_reg |= mask;
 		I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
 		(void) I915_READ(DEIMR);
+		dev_priv->de_irq_enable_reg &= ~mask;
+		I915_WRITE(DEIER, dev_priv->de_irq_enable_reg);
+		(void) I915_READ(DEIER);
 	}
 }
 
-- 
1.5.4.5