[Intel-gfx] [PATCH] drm/i915: use native backlight control in opregion backlight handler

[Li Peng]

It maps backlight value (0~255) in opregion ASLE[BCLP] to native
backlight duty cycle (0~max_backlight) and set into control register.
It also add support for IGD device, which follows opregion spec.

Signed-off-by: Li Peng <peng.li at intel.com>
---
 drivers/gpu/drm/i915/i915_opregion.c |   24 +++++++++++++++---------
 1 files changed, 15 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_opregion.c b/drivers/gpu/drm/i915/i915_opregion.c
index e4b4e88..30b6a82 100644
--- a/drivers/gpu/drm/i915/i915_opregion.c
+++ b/drivers/gpu/drm/i915/i915_opregion.c
@@ -147,7 +147,8 @@ static u32 asle_set_backlight(struct drm_device *dev, u32 bclp)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct opregion_asle *asle = dev_priv->opregion.asle;
-	u32 blc_pwm_ctl, blc_pwm_ctl2;
+	u32 blc_pwm_ctl;
+	u32 max_backlight, level, shift;
 
 	if (!(bclp & ASLE_BCLP_VALID))
 		return ASLE_BACKLIGHT_FAIL;
@@ -157,14 +158,19 @@ static u32 asle_set_backlight(struct drm_device *dev, u32 bclp)
 		return ASLE_BACKLIGHT_FAIL;
 
 	blc_pwm_ctl = I915_READ(BLC_PWM_CTL);
-	blc_pwm_ctl &= ~BACKLIGHT_DUTY_CYCLE_MASK;
-	blc_pwm_ctl2 = I915_READ(BLC_PWM_CTL2);
-
-	if (blc_pwm_ctl2 & BLM_COMBINATION_MODE)
-		pci_write_config_dword(dev->pdev, PCI_LBPC, bclp);
-	else
-		I915_WRITE(BLC_PWM_CTL, blc_pwm_ctl | ((bclp * 0x101)-1));
-
+	if (IS_IGD(dev)) {
+		blc_pwm_ctl &= ~(BACKLIGHT_DUTY_CYCLE_MASK - 1);
+		max_backlight = ((blc_pwm_ctl & BACKLIGHT_MODULATION_FREQ_MASK) >> 
+				BACKLIGHT_MODULATION_FREQ_SHIFT);
+		shift = BACKLIGHT_DUTY_CYCLE_SHIFT + 1;
+	} else {
+		blc_pwm_ctl &= ~BACKLIGHT_DUTY_CYCLE_MASK;
+		max_backlight = ((blc_pwm_ctl & BACKLIGHT_MODULATION_FREQ_MASK) >> 
+				BACKLIGHT_MODULATION_FREQ_SHIFT) * 2;
+		shift = BACKLIGHT_DUTY_CYCLE_SHIFT;
+	}
+	level = (bclp * max_backlight) / 255;
+	I915_WRITE(BLC_PWM_CTL, (blc_pwm_ctl | (level << shift)));
 	asle->cblv = (bclp*0x64)/0xff | ASLE_CBLV_VALID;
 
 	return 0;
-- 
1.6.1.3