[Intel-gfx] [PATCH] strange args for intel_calculate_wm in pineview function

[Daniel Vetter]

Hi Jesse,

This is something I've stumbled upon while crawling through code. Passing
a fifo line size instead of a latency is surely not what's ment to happen.
Can you please take a look? I think the below patch makes somewhat sense.

Yours, Daniel
---
 drivers/gpu/drm/i915/intel_display.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 9cd6de5..34e2c3a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2482,8 +2482,8 @@ static void pineview_enable_cxsr(struct drm_device *dev, unsigned long clock,
 	I915_WRITE(DSPFW3, reg);
 
 	/* Display HPLL off SR */
-	wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
-		latency->display_hpll_disable, I915_FIFO_LINE_SIZE);
+	wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm, pixel_size,
+				latency->display_hpll_disable);
 	reg = I915_READ(DSPFW3);
 	reg &= 0xfffffe00;
 	reg |= wm & 0x1ff;
-- 
1.7.0.4