[Intel-gfx] [PATCH] strange args for intel_calculate_wm in pineview function

[ykzhao]

On Sun, 2010-04-18 at 05:05 +0800, Daniel Vetter wrote:
> Hi Jesse,

Hi, Daniel
    Thanks for catching this issue. Yes. The incorrect parameter is used
to calculate the watermark for HPLL down.

    In fact now the HPLL down is not enabled on pineview platform. So it
doesn't matter even when we get the incorrect watermark for HPLL down. 
Anyway, thanks for catching this issue and the fix patch.
    
BTW: this issue is already fixed in the following commit in
drm-intel-next tree.
   >commit d4294342fd4b94a3297867da00c1c5e929c28d4f
Author: Zhao Yakui <yakui.zhao at intel.com>
Date:   Mon Mar 22 22:45:36 2010 +0800

    drm/i915: Move Pineview CxSR and watermark code into update_wm hook.

Thanks.
    Yakui
        

> 
> This is something I've stumbled upon while crawling through code. Passing
> a fifo line size instead of a latency is surely not what's ment to happen.
> Can you please take a look? I think the below patch makes somewhat sense.
> 
> Yours, Daniel
> ---
>  drivers/gpu/drm/i915/intel_display.c |    4 ++--
>  1 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 9cd6de5..34e2c3a 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2482,8 +2482,8 @@ static void pineview_enable_cxsr(struct drm_device *dev, unsigned long clock,
>  	I915_WRITE(DSPFW3, reg);
>  
>  	/* Display HPLL off SR */
> -	wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
> -		latency->display_hpll_disable, I915_FIFO_LINE_SIZE);
> +	wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm, pixel_size,
> +				latency->display_hpll_disable);
>  	reg = I915_READ(DSPFW3);
>  	reg &= 0xfffffe00;
>  	reg |= wm & 0x1ff;