[Intel-gfx] [PATCH 4/5] drm/i915: use PIPE_CONTROL for GEM domain flushing

[Jesse Barnes]

This gives us finer grained cache control, so should be higher performance.

Signed-off-by: Jesse Barnes <jbarnes at virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_gem.c |   52 +++++++++++++++++++++++++++++---------
 1 files changed, 39 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 21bfaae..e6a1cc0 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1983,29 +1983,55 @@ i915_gem_flush(struct drm_device *dev,
 		 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
 		 * are flushed at any MI_FLUSH.
 		 */
+		if (HAS_PIPE_CONTROL(dev)) {
+			cmd = GFX_OP_PIPE_CONTROL;
 
-		cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
-		if ((invalidate_domains|flush_domains) &
-		    I915_GEM_DOMAIN_RENDER)
-			cmd &= ~MI_NO_WRITE_FLUSH;
-		if (!IS_I965G(dev)) {
+			/*
+			 * Different chips support different flush bits, so
+			 * be careful here.  See 3D pipeline volume for
+			 * flush tables.
+			 */
+			if ((invalidate_domains|flush_domains) &
+			    I915_GEM_DOMAIN_RENDER)
+				cmd |= PIPE_CONTROL_WC_FLUSH;
+
+			if ((IS_G4X(dev) || IS_IRONLAKE(dev)) &&
+			    invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
+				cmd |= PIPE_CONTROL_TC_FLUSH;
+
+			if (!IS_IRONLAKE(dev) &&
+			    invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
+				cmd |= PIPE_CONTROL_IS_FLUSH;
+
+			BEGIN_LP_RING(4);
+			OUT_RING(cmd);
+			OUT_RING(0); /* unused addr */
+			OUT_RING(0); /* unused data */
+			OUT_RING(0); /* unused data */
+			ADVANCE_LP_RING();
+		} else {
+			cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
+			if ((invalidate_domains|flush_domains) &
+			    I915_GEM_DOMAIN_RENDER)
+				cmd &= ~MI_NO_WRITE_FLUSH;
 			/*
 			 * On the 965, the sampler cache always gets flushed
 			 * and this bit is reserved.
 			 */
 			if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
 				cmd |= MI_READ_FLUSH;
-		}
-		if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
-			cmd |= MI_EXE_FLUSH;
+			if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
+				cmd |= MI_EXE_FLUSH;
 
 #if WATCH_EXEC
-		DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
+			DRM_INFO("%s: queue flush %08x to ring\n", __func__,
+				 cmd);
 #endif
-		BEGIN_LP_RING(2);
-		OUT_RING(cmd);
-		OUT_RING(MI_NOOP);
-		ADVANCE_LP_RING();
+			BEGIN_LP_RING(2);
+			OUT_RING(cmd);
+			OUT_RING(MI_NOOP);
+			ADVANCE_LP_RING();
+		}
 	}
 }
 
-- 
1.7.0.1