[Intel-gfx] [PATCH 3/5] drm/i915: use PIPE_CONTROL to retire commands

[Eric Anholt]

On Wed, 21 Apr 2010 11:39:24 -0700, Jesse Barnes <jbarnes at virtuousgeek.org> wrote:
> This allows us to do less cache flushing on 965+ chipsets.

I don't think this commit is correct.  The ring processing will continue
past the PIPE_CONTROL and on to the MI_USER_INTERRUPT before the
pipeline is flushed.

I suspect that squashing this with later commits may make for a correct
change, though.
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